Maksim Kiselev f4bf0b909a clk: thead: Fix TH1520 emmc and shdci clock rate ... In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci is 198Mhz which is got through frequency division of source clock VIDEO PLL by 4 [1]. But now the AP_SUBSYS driver sets the CLK EMMC SDIO to the same frequency as the VIDEO PLL, equal to 792 MHz. This causes emmc/sdhci to work 4 times slower. Let's fix this issue by adding fixed factor clock that divides VIDEO PLL by 4 for emmc/sdhci. Link: 7563179071/drivers/clk/thead/clk-light-fm.c (L454) Fixes: ae81b69fd2 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks") Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Link: https://lore.kernel.org/r/20241210083029.92620-1-bigunclemax@gmail.com Tested-by: Xi Ruoyao <xry111@xry111.site> Reviewed-by: Drew Fustini <dfustini@tenstorrent.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2024-12-17 12:17:50 -08:00
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clk-th1520-ap.c	clk: thead: Fix TH1520 emmc and shdci clock rate	2024-12-17 12:17:50 -08:00
Kconfig	clk: T-Head: Disable on 32-bit Targets	2024-07-22 14:29:23 -07:00
Makefile