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b4cbe606dc
Add support for common interface of the common clock and reset driver for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL, and the PISMU provides clock and reset functionality. Each drivers are provided in this patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp [sboyd@kernel.org: Add bitfield.h include to pll.c] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Toshiba Visconti ARM SoC reset controller
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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* Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "reset.h"
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static inline struct visconti_reset *to_visconti_reset(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct visconti_reset, rcdev);
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}
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static int visconti_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct visconti_reset *reset = to_visconti_reset(rcdev);
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const struct visconti_reset_data *data = &reset->resets[id];
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u32 rst = BIT(data->rs_idx);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(reset->lock, flags);
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ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst);
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spin_unlock_irqrestore(reset->lock, flags);
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return ret;
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}
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static int visconti_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct visconti_reset *reset = to_visconti_reset(rcdev);
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const struct visconti_reset_data *data = &reset->resets[id];
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u32 rst = BIT(data->rs_idx);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(reset->lock, flags);
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ret = regmap_update_bits(reset->regmap, data->rsoff_offset, rst, rst);
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spin_unlock_irqrestore(reset->lock, flags);
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return ret;
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}
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static int visconti_reset_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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visconti_reset_assert(rcdev, id);
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udelay(1);
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visconti_reset_deassert(rcdev, id);
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return 0;
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}
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static int visconti_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct visconti_reset *reset = to_visconti_reset(rcdev);
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const struct visconti_reset_data *data = &reset->resets[id];
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unsigned long flags;
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u32 reg;
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int ret;
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spin_lock_irqsave(reset->lock, flags);
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ret = regmap_read(reset->regmap, data->rson_offset, ®);
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spin_unlock_irqrestore(reset->lock, flags);
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if (ret)
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return ret;
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return !(reg & data->rs_idx);
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}
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const struct reset_control_ops visconti_reset_ops = {
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.assert = visconti_reset_assert,
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.deassert = visconti_reset_deassert,
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.reset = visconti_reset_reset,
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.status = visconti_reset_status,
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};
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int visconti_register_reset_controller(struct device *dev,
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struct regmap *regmap,
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const struct visconti_reset_data *resets,
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unsigned int num_resets,
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const struct reset_control_ops *reset_ops,
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spinlock_t *lock)
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{
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struct visconti_reset *reset;
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reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
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if (!reset)
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return -ENOMEM;
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reset->regmap = regmap;
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reset->resets = resets;
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reset->rcdev.ops = reset_ops;
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reset->rcdev.nr_resets = num_resets;
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reset->rcdev.of_node = dev->of_node;
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reset->lock = lock;
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return devm_reset_controller_register(dev, &reset->rcdev);
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}
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