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https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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baf4ae8038
- Add virtual cpufreq driver for guest kernels (David Dai). - Minor cleanup to various cpufreq drivers (Andy Shevchenko, Dhruva Gole, Jie Zhan, Jinjie Ruan, Shuosheng Huang, Sibi Sankar, and Yuan Can). - Revert "cpufreq: brcmstb-avs-cpufreq: Fix initial command check" (Colin Ian King). - Improve DT bindings for qcom-hw driver (Dmitry Baryshkov, Konrad Dybcio, and Nikunj Kela). -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEx73Crsp7f6M6scA70rkcPK6BEhwFAmc6wgAACgkQ0rkcPK6B Ehz2HA/9FvaDMmi4q1yt2CvkypN4XiaerUZBE+wBMgLDiGIOzx3X1YpiZwfH7LRR V+E7+63ZYH0bxfErG3M75x8YKvARB5WaiP+f+YYIFGnBiNdbG8WdooAy+gViE+AX Wiq4FNV2IqaQXceq1TCFMiwN8tn1gZO/axsWDiEUB+bTn11noJBkNa4I6TaGDH4X IwTVss5VBcP4fORmkTSnA/Epw6mtFIQfHPO3m5SbgBiB6NVK3+//ZAnHCYB23H34 X5f0BcTw0IxkHbSuASg8ZMgqHfnmduV8g8dAhhIMkh2Zci145nmcSdcBZk1G32NC ffYznTTwEVRGMQ9ku6j9FXrqUw0Bb8GEOKSNMoO0Tc+e0UmAP/xKYICH3lbLEfXo 3DWBDNu7wNjTpZ5OJwkFsRspCVZVBDi/bnBH+XN2ELzLIPiSMN2R+I480G5uNfMt iLy9Vzqpw7H6Z2OZiN9scUDZ/pgIC7T3ZjJLwy6XsBeWjM3/AwNPx1LYM5UNFl2P MEQs0EOXl1jxMEFG4jmr8iDT5dhgX0LM5zVq0kK/dQCtLtz9BqcVr3NV3bU4pLrx fldHqaxZXnCFqtXR3RHSodGdj1B3H+KhgeXki7qxtXAAzdydNFDZxA0Kxm7DHG0i onwB+b+J4TrEIwdAODZsjh4XYjKl/fLaIinHCkabQhOXUlQsgcg= =72Nq -----END PGP SIGNATURE----- Merge tag 'cpufreq-arm-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm Merge ARM cpufreq updates for 6.13 from Viresh Kumar: "- Add virtual cpufreq driver for guest kernels (David Dai). - Minor cleanup to various cpufreq drivers (Andy Shevchenko, Dhruva Gole, Jie Zhan, Jinjie Ruan, Shuosheng Huang, Sibi Sankar, and Yuan Can). - Revert "cpufreq: brcmstb-avs-cpufreq: Fix initial command check" (Colin Ian King). - Improve DT bindings for qcom-hw driver (Dmitry Baryshkov, Konrad Dybcio, and Nikunj Kela)." * tag 'cpufreq-arm-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: arm64: dts: qcom: sc8180x: Add a SoC-specific compatible to cpufreq-hw dt-bindings: cpufreq: cpufreq-qcom-hw: Add SC8180X compatible cpufreq: sun50i: add a100 cpufreq support cpufreq: mediatek-hw: Fix wrong return value in mtk_cpufreq_get_cpu_power() cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_power() cpufreq: CPPC: Fix wrong return value in cppc_get_cpu_cost() cpufreq: loongson3: Check for error code from devm_mutex_init() call cpufreq: scmi: Fix cleanup path when boost enablement fails cpufreq: CPPC: Fix possible null-ptr-deref for cppc_get_cpu_cost() cpufreq: CPPC: Fix possible null-ptr-deref for cpufreq_cpu_get_raw() Revert "cpufreq: brcmstb-avs-cpufreq: Fix initial command check" dt-bindings: cpufreq: cpufreq-qcom-hw: Add SAR2130P compatible cpufreq: add virtual-cpufreq driver dt-bindings: cpufreq: add virtual cpufreq device cpufreq: loongson2: Unregister platform_driver on failure cpufreq: ti-cpufreq: Remove revision offsets in AM62 family cpufreq: ti-cpufreq: Allow backward compatibility for efuse syscon cppc_cpufreq: Remove HiSilicon CPPC workaround cppc_cpufreq: Use desired perf if feedback ctrs are 0 or unchanged dt-bindings: cpufreq: qcom-hw: document support for SA8255p
375 lines
8.4 KiB
C
375 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Allwinner CPUFreq nvmem based driver
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*
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* The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
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* provide the OPP framework with required information.
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*
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* Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/arm-smccc.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#define NVMEM_MASK 0x7
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#define NVMEM_SHIFT 5
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#define SUN50I_A100_NVMEM_MASK 0xf
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#define SUN50I_A100_NVMEM_SHIFT 12
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static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
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struct sunxi_cpufreq_data {
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u32 (*efuse_xlate)(u32 speedbin);
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};
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static u32 sun50i_h6_efuse_xlate(u32 speedbin)
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{
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u32 efuse_value;
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efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
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/*
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* We treat unexpected efuse values as if the SoC was from
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* the slowest bin. Expected efuse values are 1-3, slowest
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* to fastest.
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*/
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if (efuse_value >= 1 && efuse_value <= 3)
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return efuse_value - 1;
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else
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return 0;
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}
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static u32 sun50i_a100_efuse_xlate(u32 speedbin)
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{
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u32 efuse_value;
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efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
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SUN50I_A100_NVMEM_MASK;
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switch (efuse_value) {
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case 0b100:
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return 2;
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case 0b010:
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return 1;
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default:
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return 0;
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}
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}
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static int get_soc_id_revision(void)
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{
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#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
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return arm_smccc_get_soc_id_revision();
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#else
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return SMCCC_RET_NOT_SUPPORTED;
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#endif
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}
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/*
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* Judging by the OPP tables in the vendor BSP, the quality order of the
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* returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
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* 0 and 2 seem identical from the OPP tables' point of view.
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*/
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static u32 sun50i_h616_efuse_xlate(u32 speedbin)
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{
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int ver_bits = get_soc_id_revision();
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u32 value = 0;
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switch (speedbin & 0xffff) {
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case 0x2000:
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value = 0;
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break;
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case 0x2400:
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case 0x7400:
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case 0x2c00:
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case 0x7c00:
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if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) {
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/* ic version A/B */
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value = 1;
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} else {
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/* ic version C and later version */
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value = 2;
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}
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break;
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case 0x5000:
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case 0x5400:
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case 0x6000:
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value = 3;
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break;
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case 0x5c00:
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value = 4;
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break;
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case 0x5d00:
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value = 0;
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break;
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case 0x6c00:
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value = 5;
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break;
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default:
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pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",
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speedbin & 0xffff);
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value = 0;
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break;
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}
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return value;
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}
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static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
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.efuse_xlate = sun50i_h6_efuse_xlate,
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};
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static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
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.efuse_xlate = sun50i_a100_efuse_xlate,
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};
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static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
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.efuse_xlate = sun50i_h616_efuse_xlate,
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};
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static const struct of_device_id cpu_opp_match_list[] = {
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{ .compatible = "allwinner,sun50i-h6-operating-points",
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.data = &sun50i_h6_cpufreq_data,
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},
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{ .compatible = "allwinner,sun50i-a100-operating-points",
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.data = &sun50i_a100_cpufreq_data,
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},
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{ .compatible = "allwinner,sun50i-h616-operating-points",
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.data = &sun50i_h616_cpufreq_data,
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},
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{}
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};
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/**
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* dt_has_supported_hw() - Check if any OPPs use opp-supported-hw
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*
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* If we ask the cpufreq framework to use the opp-supported-hw feature, it
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* will ignore every OPP node without that DT property. If none of the OPPs
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* have it, the driver will fail probing, due to the lack of OPPs.
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*
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* Returns true if we have at least one OPP with the opp-supported-hw property.
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*/
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static bool dt_has_supported_hw(void)
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{
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bool has_opp_supported_hw = false;
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struct device *cpu_dev;
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev)
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return false;
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struct device_node *np __free(device_node) =
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dev_pm_opp_of_get_opp_desc_node(cpu_dev);
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if (!np)
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return false;
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for_each_child_of_node_scoped(np, opp) {
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if (of_property_present(opp, "opp-supported-hw")) {
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has_opp_supported_hw = true;
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break;
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}
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}
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return has_opp_supported_hw;
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}
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/**
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* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
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*
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* Returns non-negative speed bin index on success, a negative error
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* value otherwise.
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*/
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static int sun50i_cpufreq_get_efuse(void)
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{
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const struct sunxi_cpufreq_data *opp_data;
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struct nvmem_cell *speedbin_nvmem;
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const struct of_device_id *match;
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struct device *cpu_dev;
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u32 *speedbin;
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int ret;
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cpu_dev = get_cpu_device(0);
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if (!cpu_dev)
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return -ENODEV;
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struct device_node *np __free(device_node) =
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dev_pm_opp_of_get_opp_desc_node(cpu_dev);
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if (!np)
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return -ENOENT;
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match = of_match_node(cpu_opp_match_list, np);
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if (!match)
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return -ENOENT;
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opp_data = match->data;
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speedbin_nvmem = of_nvmem_cell_get(np, NULL);
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if (IS_ERR(speedbin_nvmem))
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return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
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"Could not get nvmem cell\n");
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speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
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nvmem_cell_put(speedbin_nvmem);
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if (IS_ERR(speedbin))
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return PTR_ERR(speedbin);
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ret = opp_data->efuse_xlate(*speedbin);
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kfree(speedbin);
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return ret;
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};
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static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
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{
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int *opp_tokens;
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char name[] = "speedXXXXXXXXXXX"; /* Integers can take 11 chars max */
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unsigned int cpu, supported_hw;
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struct dev_pm_opp_config config = {};
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int speed;
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int ret;
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opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
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GFP_KERNEL);
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if (!opp_tokens)
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return -ENOMEM;
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speed = sun50i_cpufreq_get_efuse();
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if (speed < 0) {
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kfree(opp_tokens);
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return speed;
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}
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/*
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* We need at least one OPP with the "opp-supported-hw" property,
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* or else the upper layers will ignore every OPP and will bail out.
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*/
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if (dt_has_supported_hw()) {
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supported_hw = 1U << speed;
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config.supported_hw = &supported_hw;
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config.supported_hw_count = 1;
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}
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snprintf(name, sizeof(name), "speed%d", speed);
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config.prop_name = name;
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for_each_possible_cpu(cpu) {
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struct device *cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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ret = -ENODEV;
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goto free_opp;
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}
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ret = dev_pm_opp_set_config(cpu_dev, &config);
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if (ret < 0)
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goto free_opp;
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opp_tokens[cpu] = ret;
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}
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cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
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NULL, 0);
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if (!IS_ERR(cpufreq_dt_pdev)) {
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platform_set_drvdata(pdev, opp_tokens);
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return 0;
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}
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ret = PTR_ERR(cpufreq_dt_pdev);
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pr_err("Failed to register platform device\n");
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free_opp:
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for_each_possible_cpu(cpu)
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dev_pm_opp_clear_config(opp_tokens[cpu]);
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kfree(opp_tokens);
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return ret;
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}
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static void sun50i_cpufreq_nvmem_remove(struct platform_device *pdev)
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{
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int *opp_tokens = platform_get_drvdata(pdev);
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unsigned int cpu;
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platform_device_unregister(cpufreq_dt_pdev);
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for_each_possible_cpu(cpu)
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dev_pm_opp_clear_config(opp_tokens[cpu]);
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kfree(opp_tokens);
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}
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static struct platform_driver sun50i_cpufreq_driver = {
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.probe = sun50i_cpufreq_nvmem_probe,
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.remove = sun50i_cpufreq_nvmem_remove,
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.driver = {
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.name = "sun50i-cpufreq-nvmem",
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},
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};
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static const struct of_device_id sun50i_cpufreq_match_list[] = {
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{ .compatible = "allwinner,sun50i-h6" },
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{ .compatible = "allwinner,sun50i-a100" },
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{ .compatible = "allwinner,sun50i-h616" },
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{ .compatible = "allwinner,sun50i-h618" },
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{ .compatible = "allwinner,sun50i-h700" },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
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static const struct of_device_id *sun50i_cpufreq_match_node(void)
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{
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struct device_node *np __free(device_node) = of_find_node_by_path("/");
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return of_match_node(sun50i_cpufreq_match_list, np);
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}
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/*
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* Since the driver depends on nvmem drivers, which may return EPROBE_DEFER,
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* all the real activity is done in the probe, which may be defered as well.
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* The init here is only registering the driver and the platform device.
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*/
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static int __init sun50i_cpufreq_init(void)
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{
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const struct of_device_id *match;
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int ret;
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match = sun50i_cpufreq_match_node();
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if (!match)
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return -ENODEV;
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ret = platform_driver_register(&sun50i_cpufreq_driver);
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if (unlikely(ret < 0))
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return ret;
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sun50i_cpufreq_pdev =
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platform_device_register_simple("sun50i-cpufreq-nvmem",
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-1, NULL, 0);
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ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
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if (ret == 0)
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return 0;
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platform_driver_unregister(&sun50i_cpufreq_driver);
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return ret;
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}
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module_init(sun50i_cpufreq_init);
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static void __exit sun50i_cpufreq_exit(void)
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{
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platform_device_unregister(sun50i_cpufreq_pdev);
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platform_driver_unregister(&sun50i_cpufreq_driver);
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}
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module_exit(sun50i_cpufreq_exit);
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MODULE_DESCRIPTION("Sun50i-h6 cpufreq driver");
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MODULE_LICENSE("GPL v2");
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