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1ad3f701c3
CXL PMU devices can be found from entries in the Register Locator DVSEC. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230526095824.16336-4-Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
29 lines
656 B
C
29 lines
656 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright(c) 2023 Huawei
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* CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface)
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*/
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#ifndef CXL_PMU_H
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#define CXL_PMU_H
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#include <linux/device.h>
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enum cxl_pmu_type {
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CXL_PMU_MEMDEV,
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};
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#define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */
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struct cxl_pmu {
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struct device dev;
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void __iomem *base;
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int assoc_id;
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int index;
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enum cxl_pmu_type type;
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};
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#define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev)
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struct cxl_pmu_regs;
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int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs,
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int assoc_id, int idx, enum cxl_pmu_type type);
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#endif
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