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68682e9578
Introduce device driver for PCIe implementation of RISC-V IOMMU architected hardware. IOMMU hardware and system support for MSI or MSI-X is required by this implementation. Vendor and device identifiers used in this patch matches QEMU implementation of the RISC-V IOMMU PCIe device, from Rivos VID (0x1efd) range allocated by the PCI-SIG. MAINTAINERS | added iommu-pci.c already covered by matching pattern. Link: https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@ventanamicro.com/ Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/12f3bdbe519ebb7ca482191e7334d38b25b8ae8f.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
21 lines
620 B
Plaintext
21 lines
620 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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# RISC-V IOMMU support
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config RISCV_IOMMU
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bool "RISC-V IOMMU Support"
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depends on RISCV && 64BIT
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default y
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select IOMMU_API
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help
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Support for implementations of the RISC-V IOMMU architecture that
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complements the RISC-V MMU capabilities, providing similar address
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translation and protection functions for accesses from I/O devices.
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Say Y here if your SoC includes an IOMMU device implementing
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the RISC-V IOMMU architecture.
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config RISCV_IOMMU_PCI
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def_bool y if RISCV_IOMMU && PCI_MSI
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help
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Support for the PCIe implementation of RISC-V IOMMU architecture.
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