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e1dce56443
PCI Express Interface PMU includes various performance counters to monitor the data that is transmitted over the PCIe link. The counters track various inbound and outbound transactions which includes separate counters for posted/non-posted/completion TLPs. Also, inbound and outbound memory read requests along with their latencies can also be monitored. Address Translation Services(ATS)events such as ATS Translation, ATS Page Request, ATS Invalidation along with their corresponding latencies are also supported. The performance counters are 64 bits wide. For instance, perf stat -e ib_tlp_pr <workload> tracks the inbound posted TLPs for the workload. Co-developed-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com> Link: https://lore.kernel.org/r/20241028055309.17893-1-gthiagarajan@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
295 lines
8.8 KiB
Plaintext
295 lines
8.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Performance Monitor Drivers
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#
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menu "Performance monitor support"
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depends on PERF_EVENTS
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config ARM_CCI_PMU
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tristate "ARM CCI PMU driver"
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depends on (ARM && CPU_V7) || ARM64
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select ARM_CCI
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help
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Support for PMU events monitoring on the ARM CCI (Cache Coherent
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Interconnect) family of products.
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If compiled as a module, it will be called arm-cci.
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config ARM_CCI400_PMU
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bool "support CCI-400"
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default y
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depends on ARM_CCI_PMU
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select ARM_CCI400_COMMON
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help
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CCI-400 provides 4 independent event counters counting events related
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to the connected slave/master interfaces, plus a cycle counter.
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config ARM_CCI5xx_PMU
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bool "support CCI-500/CCI-550"
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default y
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depends on ARM_CCI_PMU
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help
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CCI-500/CCI-550 both provide 8 independent event counters, which can
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count events pertaining to the slave/master interfaces as well as the
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internal events to the CCI.
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config ARM_CCN
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tristate "ARM CCN driver support"
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depends on ARM || ARM64 || COMPILE_TEST
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help
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PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
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interconnect.
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config ARM_CMN
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tristate "Arm CMN-600 PMU support"
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depends on ARM64 || COMPILE_TEST
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help
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Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
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Network interconnect.
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config ARM_NI
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tristate "Arm NI-700 PMU support"
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depends on ARM64 || COMPILE_TEST
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help
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Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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interconnect and family.
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config ARM_PMU
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depends on ARM || ARM64
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bool "ARM PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on ARM-based
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systems.
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config ARM_V6_PMU
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depends on ARM_PMU && (CPU_V6 || CPU_V6K)
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def_bool y
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config ARM_V7_PMU
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depends on ARM_PMU && CPU_V7
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def_bool y
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config ARM_XSCALE_PMU
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depends on ARM_PMU && CPU_XSCALE
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def_bool y
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config RISCV_PMU
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depends on RISCV
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bool "RISC-V PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on RISCV-based
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systems. This provides the core PMU framework that abstracts common
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PMU functionalities in a core library so that different PMU drivers
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can reuse it.
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config RISCV_PMU_LEGACY
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depends on RISCV_PMU
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bool "RISC-V legacy PMU implementation"
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default y
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help
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Say y if you want to use the legacy CPU performance monitor
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implementation on RISC-V based systems. This only allows counting
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of cycle/instruction counter and doesn't support counter overflow,
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or programmable counters. It will be removed in future.
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config RISCV_PMU_SBI
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depends on RISCV_PMU && RISCV_SBI
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bool "RISC-V PMU based on SBI PMU extension"
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default y
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help
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Say y if you want to use the CPU performance monitor
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using SBI PMU extension on RISC-V based systems. This option provides
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full perf feature support i.e. counter overflow, privilege mode
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filtering, counter configuration.
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config STARFIVE_STARLINK_PMU
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depends on ARCH_STARFIVE || COMPILE_TEST
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depends on 64BIT
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bool "StarFive StarLink PMU"
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help
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Provide support for StarLink Performance Monitor Unit.
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StarLink Performance Monitor Unit integrates one or more cores with
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an L3 memory system. The L3 cache events are added into perf event
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subsystem, allowing monitoring of various L3 cache perf events.
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config ANDES_CUSTOM_PMU
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bool "Andes custom PMU support"
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depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
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default y
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help
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The Andes cores implement the PMU overflow extension very
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similar to the standard Sscofpmf and Smcntrpmf extension.
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This will patch the overflow and pending CSRs and handle the
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non-standard behaviour via the regular SBI PMU driver and
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interface.
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If you don't know what to do here, say "Y".
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config ARM_PMU_ACPI
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depends on ARM_PMU && ACPI
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def_bool y
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config ARM_SMMU_V3_PMU
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tristate "ARM SMMUv3 Performance Monitors Extension"
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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depends on GENERIC_MSI_IRQ
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help
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Provides support for the ARM SMMUv3 Performance Monitor Counter
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Groups (PMCG), which provide monitoring of transactions passing
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through the SMMU and allow the resulting information to be filtered
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based on the Stream ID of the corresponding master.
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config ARM_PMUV3
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depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64)
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bool "ARM PMUv3 support" if !ARM64
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default ARM64
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help
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Say y if you want to use the ARM performance monitor unit (PMU)
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version 3. The PMUv3 is the CPU performance monitors on ARMv8
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(aarch32 and aarch64) systems that implement the PMUv3
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architecture.
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config ARM_DSU_PMU
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tristate "ARM DynamIQ Shared Unit (DSU) PMU"
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depends on ARM64
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help
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Provides support for performance monitor unit in ARM DynamIQ Shared
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Unit (DSU). The DSU integrates one or more cores with an L3 memory
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system, control logic. The PMU allows counting various events related
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to DSU.
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config FSL_IMX8_DDR_PMU
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tristate "Freescale i.MX8 DDR perf monitor"
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depends on ARCH_MXC || COMPILE_TEST
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help
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Provides support for the DDR performance monitor in i.MX8, which
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can give information about memory throughput and other related
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events.
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config FSL_IMX9_DDR_PMU
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tristate "Freescale i.MX9 DDR perf monitor"
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depends on ARCH_MXC
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help
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Provides support for the DDR performance monitor in i.MX9, which
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can give information about memory throughput and other related
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events.
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_KRYO_L2_ACCESSORS
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L2 cache PMU into the perf events subsystem for
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monitoring L2 cache events.
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config QCOM_L3_PMU
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bool "Qualcomm Technologies L3-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_IRQ_COMBINER
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help
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Provides support for the L3 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L3 cache PMU into the perf events subsystem for
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monitoring L3 cache events.
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config THUNDERX2_PMU
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tristate "Cavium ThunderX2 SoC PMU UNCORE"
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depends on ARCH_THUNDER2 || COMPILE_TEST
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depends on NUMA && ACPI
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default m
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help
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Provides support for ThunderX2 UNCORE events.
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The SoC has PMU support in its L3 cache controller (L3C) and
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in the DDR4 Memory Controller (DMC).
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config XGENE_PMU
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depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
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bool "APM X-Gene SoC PMU"
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default n
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help
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Say y if you want to use APM X-Gene SoC performance monitors.
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config ARM_SPE_PMU
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tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
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depends on ARM64
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help
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Enable perf support for the ARMv8.2 Statistical Profiling
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Extension, which provides periodic sampling of operations in
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the CPU pipeline and reports this via the perf AUX interface.
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config ARM_DMC620_PMU
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tristate "Enable PMU support for the ARM DMC-620 memory controller"
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depends on (ARM64 && ACPI) || COMPILE_TEST
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help
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Support for PMU events monitoring on the ARM DMC-620 memory
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controller.
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config MARVELL_CN10K_TAD_PMU
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tristate "Marvell CN10K LLC-TAD PMU"
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depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
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help
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Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
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performance monitors on CN10K family silicons.
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config APPLE_M1_CPU_PMU
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bool "Apple M1 CPU PMU support"
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depends on ARM_PMU && ARCH_APPLE
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help
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Provides support for the non-architectural CPU PMUs present on
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the Apple M1 SoCs and derivatives.
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config ALIBABA_UNCORE_DRW_PMU
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tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
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depends on (ARM64 && ACPI) || COMPILE_TEST
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help
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Support for Driveway PMU events monitoring on Yitian 710 DDR
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Sub-system.
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source "drivers/perf/hisilicon/Kconfig"
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config MARVELL_CN10K_DDR_PMU
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tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
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depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
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help
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Enable perf support for Marvell DDR Performance monitoring
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event on CN10K platform.
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config DWC_PCIE_PMU
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tristate "Synopsys DesignWare PCIe PMU"
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depends on PCI
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help
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Enable perf support for Synopsys DesignWare PCIe PMU Performance
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monitoring event on platform including the Alibaba Yitian 710.
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source "drivers/perf/arm_cspmu/Kconfig"
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source "drivers/perf/amlogic/Kconfig"
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config CXL_PMU
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tristate "CXL Performance Monitoring Unit"
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depends on CXL_BUS
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help
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Support performance monitoring as defined in CXL rev 3.0
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section 13.2: Performance Monitoring. CXL components may have
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one or more CXL Performance Monitoring Units (CPMUs).
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Say 'y/m' to enable a driver that will attach to performance
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monitoring units and provide standard perf based interfaces.
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If unsure say 'm'.
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config MARVELL_PEM_PMU
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tristate "MARVELL PEM PMU Support"
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depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
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help
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Enable support for PCIe Interface performance monitoring
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on Marvell platform.
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endmenu
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