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4e92d50447
These register prints are useful to validate the init sequence against the Qcom internal documentation and also to share with the Qcom hw engineers to debug issues related to PHY. Sample debug prints: qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9 qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240731152548.102987-1-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
63 lines
1.2 KiB
C
63 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_COMMON_H_
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#define QCOM_PHY_QMP_COMMON_H_
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struct qmp_phy_init_tbl {
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unsigned int offset;
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unsigned int val;
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char *name;
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/*
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* mask of lanes for which this register is written
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* for cases when second lane needs different values
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*/
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u8 lane_mask;
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};
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#define QMP_PHY_INIT_CFG(o, v) \
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{ \
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.offset = o, \
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.val = v, \
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.name = #o, \
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.lane_mask = 0xff, \
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}
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#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
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{ \
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.offset = o, \
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.val = v, \
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.name = #o, \
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.lane_mask = l, \
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}
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static inline void qmp_configure_lane(struct device *dev, void __iomem *base,
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const struct qmp_phy_init_tbl tbl[],
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int num, u8 lane_mask)
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{
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int i;
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const struct qmp_phy_init_tbl *t = tbl;
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if (!t)
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return;
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for (i = 0; i < num; i++, t++) {
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if (!(t->lane_mask & lane_mask))
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continue;
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dev_dbg(dev, "Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
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t->name, t->offset, t->val);
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writel(t->val, base + t->offset);
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}
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}
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static inline void qmp_configure(struct device *dev, void __iomem *base,
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const struct qmp_phy_init_tbl tbl[], int num)
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{
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qmp_configure_lane(dev, base, tbl, num, 0xff);
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}
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#endif
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