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99bf896263
The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for
combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS
register offsets, which are different. Add the offsets so the
mentioned platform can be fixed later on. Add the new PCS offsets
in a dedicated header file.
Fixes: d7b3579f84 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_N4_H_
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#define QCOM_PHY_QMP_PCS_V6_N4_H_
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/* Only for QMP V6 N4 PHY - USB/PCIe PCS registers */
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#define QPHY_V6_N4_PCS_SW_RESET 0x000
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#define QPHY_V6_N4_PCS_PCS_STATUS1 0x014
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#define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL 0x040
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#define QPHY_V6_N4_PCS_START_CONTROL 0x044
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#define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1 0x090
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3 0x0cc
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#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6 0x0d8
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#define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V6_N4_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_V6_N4_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V6_N4_PCS_RX_CONFIG 0x1b0
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#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_V6_N4_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_V6_N4_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V6_N4_PCS_EQ_CONFIG5 0x1ec
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#endif
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