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e6550b3ee1
Based on the normalized pattern:
this program is free software you may redistribute it and/or modify it
under the terms of the gnu general public license as published by the
free software foundation version 2 of the license the software is
provided as is without warranty of any kind express or implied
including but not limited to the warranties of merchantability fitness
for a particular purpose and noninfringement in no event shall the
authors or copyright holders be liable for any claim damages or other
liability whether in an action of contract tort or otherwise arising
from out of or in connection with the software or the use or other
dealings in the software
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2008 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _VNIC_CQ_H_
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#define _VNIC_CQ_H_
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#include "cq_desc.h"
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#include "vnic_dev.h"
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/*
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* These defines avoid symbol clash between fnic and enic (Cisco 10G Eth
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* Driver) when both are built with CONFIG options =y
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*/
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#define vnic_cq_service fnic_cq_service
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#define vnic_cq_free fnic_cq_free
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#define vnic_cq_alloc fnic_cq_alloc
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#define vnic_cq_init fnic_cq_init
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#define vnic_cq_clean fnic_cq_clean
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/* Completion queue control */
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struct vnic_cq_ctrl {
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u64 ring_base; /* 0x00 */
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u32 ring_size; /* 0x08 */
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u32 pad0;
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u32 flow_control_enable; /* 0x10 */
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u32 pad1;
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u32 color_enable; /* 0x18 */
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u32 pad2;
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u32 cq_head; /* 0x20 */
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u32 pad3;
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u32 cq_tail; /* 0x28 */
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u32 pad4;
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u32 cq_tail_color; /* 0x30 */
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u32 pad5;
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u32 interrupt_enable; /* 0x38 */
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u32 pad6;
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u32 cq_entry_enable; /* 0x40 */
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u32 pad7;
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u32 cq_message_enable; /* 0x48 */
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u32 pad8;
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u32 interrupt_offset; /* 0x50 */
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u32 pad9;
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u64 cq_message_addr; /* 0x58 */
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u32 pad10;
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};
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struct vnic_cq {
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unsigned int index;
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struct vnic_dev *vdev;
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struct vnic_cq_ctrl __iomem *ctrl; /* memory-mapped */
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struct vnic_dev_ring ring;
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unsigned int to_clean;
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unsigned int last_color;
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};
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static inline unsigned int vnic_cq_service(struct vnic_cq *cq,
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unsigned int work_to_do,
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int (*q_service)(struct vnic_dev *vdev, struct cq_desc *cq_desc,
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u8 type, u16 q_number, u16 completed_index, void *opaque),
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void *opaque)
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{
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struct cq_desc *cq_desc;
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unsigned int work_done = 0;
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u16 q_number, completed_index;
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u8 type, color;
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cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +
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cq->ring.desc_size * cq->to_clean);
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cq_desc_dec(cq_desc, &type, &color,
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&q_number, &completed_index);
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while (color != cq->last_color) {
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if ((*q_service)(cq->vdev, cq_desc, type,
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q_number, completed_index, opaque))
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break;
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cq->to_clean++;
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if (cq->to_clean == cq->ring.desc_count) {
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cq->to_clean = 0;
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cq->last_color = cq->last_color ? 0 : 1;
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}
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cq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +
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cq->ring.desc_size * cq->to_clean);
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cq_desc_dec(cq_desc, &type, &color,
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&q_number, &completed_index);
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work_done++;
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if (work_done >= work_to_do)
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break;
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}
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return work_done;
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}
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void vnic_cq_free(struct vnic_cq *cq);
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int vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,
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unsigned int desc_count, unsigned int desc_size);
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void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
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unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
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unsigned int cq_tail_color, unsigned int interrupt_enable,
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unsigned int cq_entry_enable, unsigned int message_enable,
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unsigned int interrupt_offset, u64 message_addr);
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void vnic_cq_clean(struct vnic_cq *cq);
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#endif /* _VNIC_CQ_H_ */
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