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916f26f1c2
Add support for the RX2 receiver which is used as the third receiver in asymmetric links. This requires expanding the results array for the additional third data word of the hardware margining results. Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
113 lines
4.5 KiB
C
113 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* USB4 port sideband registers found on routers and retimers
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*
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* Copyright (C) 2020, Intel Corporation
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* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
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* Rajmohan Mani <rajmohan.mani@intel.com>
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*/
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#ifndef _SB_REGS
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#define _SB_REGS
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#define USB4_SB_VENDOR_ID 0x00
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#define USB4_SB_PRODUCT_ID 0x01
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#define USB4_SB_FW_VERSION 0x02
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#define USB4_SB_DEBUG_CONF 0x05
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#define USB4_SB_DEBUG 0x06
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#define USB4_SB_LRD_TUNING 0x07
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#define USB4_SB_OPCODE 0x08
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enum usb4_sb_opcode {
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USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */
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USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */
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USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */
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USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */
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USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */
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USB4_SB_OPCODE_UNSET_INBOUND_SBTX = 0x50555355, /* "USUP" */
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USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */
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USB4_SB_OPCODE_QUERY_CABLE_RETIMER = 0x524c4243, /* "CBLR" */
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USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */
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USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */
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USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */
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USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */
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USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */
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USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */
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USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */
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USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */
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USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */
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};
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#define USB4_SB_METADATA 0x09
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#define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0)
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#define USB4_SB_LINK_CONF 0x0c
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#define USB4_SB_GEN23_TXFFE 0x0d
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#define USB4_SB_GEN4_TXFFE 0x0e
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#define USB4_SB_VERSION 0x0f
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#define USB4_SB_DATA 0x12
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/* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */
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#define USB4_MARGIN_CAP_0_MODES_HW BIT(0)
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#define USB4_MARGIN_CAP_0_MODES_SW BIT(1)
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#define USB4_MARGIN_CAP_0_ALL_LANES BIT(2)
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#define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3)
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#define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x0
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#define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x1
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#define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x2
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#define USB4_MARGIN_CAP_0_TIME BIT(5)
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#define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6)
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#define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13)
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#define USB4_MARGIN_CAP_0_OPT_VOLTAGE_SUPPORT BIT(19)
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#define USB4_MARGIN_CAP_0_VOLT_STEPS_OPT_MASK GENMASK(26, 20)
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#define USB4_MARGIN_CAP_1_MAX_VOLT_OFS_OPT_MASK GENMASK(7, 0)
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#define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8)
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#define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9)
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#define USB4_MARGIN_CAP_1_TIME_MIN 0x0
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#define USB4_MARGIN_CAP_1_TIME_LR 0x1
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#define USB4_MARGIN_CAP_1_TIME_BOTH 0x2
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#define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11)
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#define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16)
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#define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21)
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#define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26)
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#define USB4_MARGIN_CAP_2_MODES_HW BIT(0)
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#define USB4_MARGIN_CAP_2_MODES_SW BIT(1)
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#define USB4_MARGIN_CAP_2_TIME BIT(2)
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#define USB4_MARGIN_CAP_2_MAX_VOLTAGE_OFFSET_MASK GENMASK(8, 3)
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#define USB4_MARGIN_CAP_2_VOLTAGE_STEPS_MASK GENMASK(15, 9)
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#define USB4_MARGIN_CAP_2_VOLTAGE_INDP_MASK GENMASK(17, 16)
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#define USB4_MARGIN_CAP_2_VOLTAGE_MIN 0x0
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#define USB4_MARGIN_CAP_2_VOLTAGE_BOTH 0x1
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#define USB4_MARGIN_CAP_2_TIME_INDP_MASK GENMASK(19, 18)
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#define USB4_MARGIN_CAP_2_TIME_MIN 0x0
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#define USB4_MARGIN_CAP_2_TIME_BOTH 0x1
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/* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */
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#define USB4_MARGIN_HW_TIME BIT(3)
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#define USB4_MARGIN_HW_RHU BIT(4)
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#define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5)
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#define USB4_MARGIN_HW_BER_SHIFT 5
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#define USB4_MARGIN_HW_OPT_VOLTAGE BIT(10)
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/* Applicable to all margin values */
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#define USB4_MARGIN_HW_RES_MARGIN_MASK GENMASK(6, 0)
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#define USB4_MARGIN_HW_RES_EXCEEDS BIT(7)
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/* Shifts for parsing the lane results */
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#define USB4_MARGIN_HW_RES_LANE_SHIFT 16
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#define USB4_MARGIN_HW_RES_LL_SHIFT 8
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/* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */
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#define USB4_MARGIN_SW_LANES_MASK GENMASK(2, 0)
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#define USB4_MARGIN_SW_TIME BIT(3)
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#define USB4_MARGIN_SW_RH BIT(4)
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#define USB4_MARGIN_SW_OPT_VOLTAGE BIT(5)
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#define USB4_MARGIN_SW_VT_MASK GENMASK(12, 6)
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#define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13)
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#define USB4_MARGIN_SW_UPPER_EYE BIT(15)
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#define USB4_MARGIN_SW_ERR_COUNTER_LANE_0_MASK GENMASK(3, 0)
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#define USB4_MARGIN_SW_ERR_COUNTER_LANE_1_MASK GENMASK(7, 4)
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#define USB4_MARGIN_SW_ERR_COUNTER_LANE_2_MASK GENMASK(11, 8)
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#endif
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