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f4d3d7340e
Add device tree bindings for global clock controller on QCS615 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
212 lines
8.0 KiB
C
212 lines
8.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
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/* GCC clocks */
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#define GPLL0_OUT_AUX2_DIV 0
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#define GPLL3_OUT_AUX2_DIV 1
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#define GPLL0 2
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#define GPLL3 3
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#define GPLL4 4
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#define GPLL6 5
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#define GPLL6_OUT_MAIN 6
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#define GPLL7 7
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#define GPLL8 8
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#define GPLL8_OUT_MAIN 9
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 10
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#define GCC_AGGRE_USB2_SEC_AXI_CLK 11
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12
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#define GCC_AHB2PHY_EAST_CLK 13
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#define GCC_AHB2PHY_WEST_CLK 14
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#define GCC_BOOT_ROM_AHB_CLK 15
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#define GCC_CAMERA_AHB_CLK 16
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#define GCC_CAMERA_HF_AXI_CLK 17
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#define GCC_CAMERA_XO_CLK 18
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#define GCC_CE1_AHB_CLK 19
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#define GCC_CE1_AXI_CLK 20
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#define GCC_CE1_CLK 21
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#define GCC_CFG_NOC_USB2_SEC_AXI_CLK 22
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
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#define GCC_CPUSS_AHB_CLK 24
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#define GCC_CPUSS_AHB_CLK_SRC 25
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#define GCC_CPUSS_GNOC_CLK 26
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#define GCC_DDRSS_GPU_AXI_CLK 27
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#define GCC_DISP_AHB_CLK 28
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 29
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#define GCC_DISP_HF_AXI_CLK 30
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#define GCC_DISP_XO_CLK 31
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#define GCC_EMAC_AXI_CLK 32
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#define GCC_EMAC_PTP_CLK 33
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#define GCC_EMAC_PTP_CLK_SRC 34
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#define GCC_EMAC_RGMII_CLK 35
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#define GCC_EMAC_RGMII_CLK_SRC 36
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#define GCC_EMAC_SLV_AHB_CLK 37
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#define GCC_GP1_CLK 38
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#define GCC_GP1_CLK_SRC 39
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#define GCC_GP2_CLK 40
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#define GCC_GP2_CLK_SRC 41
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#define GCC_GP3_CLK 42
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#define GCC_GP3_CLK_SRC 43
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#define GCC_GPU_CFG_AHB_CLK 44
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#define GCC_GPU_GPLL0_CLK_SRC 45
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 46
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#define GCC_GPU_IREF_CLK 47
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#define GCC_GPU_MEMNOC_GFX_CLK 48
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#define GCC_GPU_SNOC_DVM_GFX_CLK 49
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#define GCC_PCIE0_PHY_REFGEN_CLK 50
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#define GCC_PCIE_0_AUX_CLK 51
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#define GCC_PCIE_0_AUX_CLK_SRC 52
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#define GCC_PCIE_0_CFG_AHB_CLK 53
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#define GCC_PCIE_0_CLKREF_CLK 54
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#define GCC_PCIE_0_MSTR_AXI_CLK 55
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#define GCC_PCIE_0_PIPE_CLK 56
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#define GCC_PCIE_0_SLV_AXI_CLK 57
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58
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#define GCC_PCIE_PHY_AUX_CLK 59
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#define GCC_PCIE_PHY_REFGEN_CLK_SRC 60
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#define GCC_PDM2_CLK 61
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#define GCC_PDM2_CLK_SRC 62
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#define GCC_PDM_AHB_CLK 63
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#define GCC_PDM_XO4_CLK 64
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#define GCC_PRNG_AHB_CLK 65
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 66
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#define GCC_QMIP_DISP_AHB_CLK 67
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#define GCC_QMIP_PCIE_AHB_CLK 68
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 69
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 70
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#define GCC_QSPI_CORE_CLK 71
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#define GCC_QSPI_CORE_CLK_SRC 72
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
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#define GCC_QUPV3_WRAP0_CORE_CLK 74
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#define GCC_QUPV3_WRAP0_S0_CLK 75
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
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#define GCC_QUPV3_WRAP0_S1_CLK 77
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
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#define GCC_QUPV3_WRAP0_S2_CLK 79
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
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#define GCC_QUPV3_WRAP0_S3_CLK 81
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
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#define GCC_QUPV3_WRAP0_S4_CLK 83
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
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#define GCC_QUPV3_WRAP0_S5_CLK 85
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 87
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#define GCC_QUPV3_WRAP1_CORE_CLK 88
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#define GCC_QUPV3_WRAP1_S0_CLK 89
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_S1_CLK 91
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 92
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#define GCC_QUPV3_WRAP1_S2_CLK 93
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 94
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#define GCC_QUPV3_WRAP1_S3_CLK 95
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 96
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#define GCC_QUPV3_WRAP1_S4_CLK 97
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 98
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#define GCC_QUPV3_WRAP1_S5_CLK 99
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 100
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104
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#define GCC_RX1_USB2_CLKREF_CLK 105
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#define GCC_RX3_USB2_CLKREF_CLK 106
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#define GCC_SDCC1_AHB_CLK 107
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#define GCC_SDCC1_APPS_CLK 108
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#define GCC_SDCC1_APPS_CLK_SRC 109
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#define GCC_SDCC1_ICE_CORE_CLK 110
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 111
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#define GCC_SDCC2_AHB_CLK 112
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#define GCC_SDCC2_APPS_CLK 113
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#define GCC_SDCC2_APPS_CLK_SRC 114
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#define GCC_SDR_CORE_CLK 115
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#define GCC_SDR_CSR_HCLK 116
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#define GCC_SDR_PRI_MI2S_CLK 117
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#define GCC_SDR_SEC_MI2S_CLK 118
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#define GCC_SDR_WR0_MEM_CLK 119
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#define GCC_SDR_WR1_MEM_CLK 120
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#define GCC_SDR_WR2_MEM_CLK 121
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 122
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#define GCC_UFS_CARD_CLKREF_CLK 123
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#define GCC_UFS_MEM_CLKREF_CLK 124
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#define GCC_UFS_PHY_AHB_CLK 125
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#define GCC_UFS_PHY_AXI_CLK 126
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#define GCC_UFS_PHY_AXI_CLK_SRC 127
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#define GCC_UFS_PHY_ICE_CORE_CLK 128
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129
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#define GCC_UFS_PHY_PHY_AUX_CLK 130
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 131
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 132
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135
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#define GCC_USB20_SEC_MASTER_CLK 136
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#define GCC_USB20_SEC_MASTER_CLK_SRC 137
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#define GCC_USB20_SEC_MOCK_UTMI_CLK 138
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#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC 139
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#define GCC_USB20_SEC_SLEEP_CLK 140
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#define GCC_USB2_PRIM_CLKREF_CLK 141
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#define GCC_USB2_SEC_CLKREF_CLK 142
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#define GCC_USB2_SEC_PHY_AUX_CLK 143
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#define GCC_USB2_SEC_PHY_AUX_CLK_SRC 144
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#define GCC_USB2_SEC_PHY_COM_AUX_CLK 145
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#define GCC_USB2_SEC_PHY_PIPE_CLK 146
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#define GCC_USB30_PRIM_MASTER_CLK 147
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 148
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 149
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150
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#define GCC_USB30_PRIM_SLEEP_CLK 151
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#define GCC_USB3_PRIM_CLKREF_CLK 152
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#define GCC_USB3_PRIM_PHY_AUX_CLK 153
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 156
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#define GCC_USB3_SEC_CLKREF_CLK 157
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#define GCC_VIDEO_AHB_CLK 158
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#define GCC_VIDEO_AXI0_CLK 159
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#define GCC_VIDEO_XO_CLK 160
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#define GCC_VSENSOR_CLK_SRC 161
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 162
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 163
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 164
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 166
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/* GCC Resets */
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#define GCC_EMAC_BCR 0
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#define GCC_QUSB2PHY_PRIM_BCR 1
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#define GCC_QUSB2PHY_SEC_BCR 2
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#define GCC_USB30_PRIM_BCR 3
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#define GCC_USB2_PHY_SEC_BCR 4
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#define GCC_USB3_DP_PHY_SEC_BCR 5
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#define GCC_USB3PHY_PHY_SEC_BCR 6
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#define GCC_PCIE_0_BCR 7
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#define GCC_PCIE_0_PHY_BCR 8
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#define GCC_PCIE_PHY_BCR 9
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#define GCC_PCIE_PHY_COM_BCR 10
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#define GCC_UFS_PHY_BCR 11
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#define GCC_USB20_SEC_BCR 12
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#define GCC_USB3_PHY_PRIM_SP0_BCR 13
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 14
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#define GCC_SDCC1_BCR 15
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#define GCC_SDCC2_BCR 16
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/* GCC power domains */
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#define EMAC_GDSC 0
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#define PCIE_0_GDSC 1
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#define UFS_PHY_GDSC 2
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#define USB20_SEC_GDSC 3
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#define USB30_PRIM_GDSC 4
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#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 5
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 6
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 7
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#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 8
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 9
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 10
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
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#endif
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