Niklas Söderlund 91a7088096 media: dt-bindings: Add property to describe CSI-2 C-PHY line orders ... Each data lane on a CSI-2 C-PHY bus uses three phase encoding and is constructed from three physical wires. The wires are referred to as A, B and C and their default order is ABC. However to ease hardware design the specification allows for the wires to be switched in any order. Add a vendor neutral property to describe the line order used. The property name 'line-orders', the possible values it can be assigned and there names are taken from the MIPI Discovery and Configuration (DisCo) Specification for Imaging. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>		2024-12-19 12:50:14 +01:00
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c8sectpfe.h	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
omap3-isp.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
tda1997x.h	media: dt-bindings: Add bindings for TDA1997X	2018-02-22 12:45:42 -05:00
tvp5150.h	media: partial revert of "[media] tvp5150: add HW input connectors support"	2020-03-12 16:35:59 +01:00
video-interfaces.h	media: dt-bindings: Add property to describe CSI-2 C-PHY line orders	2024-12-19 12:50:14 +01:00
xilinx-vip.h	media: xilinx: Use SPDX-License-Identifier	2018-12-03 13:40:05 -05:00