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2025cf9e19
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 263 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
40 lines
1020 B
C
40 lines
1020 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Atom platform clocks for BayTrail and CherryTrail SoC.
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Irina Tirdea <irina.tirdea@intel.com>
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*/
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#ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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#define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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/**
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* struct pmc_clk - PMC platform clock configuration
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*
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* @name: identified, typically pmc_plt_clk_<x>, x=[0..5]
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* @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported
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* @parent_name: one of 'xtal' or 'osc'
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*/
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struct pmc_clk {
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const char *name;
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unsigned long freq;
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const char *parent_name;
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};
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/**
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* struct pmc_clk_data - common PMC clock configuration
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*
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* @base: PMC clock register base offset
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* @clks: pointer to set of registered clocks, typically 0..5
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* @critical: flag to indicate if firmware enabled pmc_plt_clks
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* should be marked as critial or not
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*/
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struct pmc_clk_data {
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void __iomem *base;
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const struct pmc_clk *clks;
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bool critical;
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};
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#endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */
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