Joakim Zhang 049d919168 drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition
When disabling a counter from ddr_perf_event_stop(), the counter value
is reset to 0 at the same time.

Preserve the counter value by performing a read-modify-write of the
PMU register and clearing only the enable bit.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-02 12:07:19 +00:00
..
2019-07-08 09:54:55 -07:00
2019-07-08 09:54:55 -07:00