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25caed3dca
Add i.MX8MP PCIe PHY binding. On i.MX8MM, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So add one more PERST explicitly for i.MX8MP PCIe PHY. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1665625622-20551-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
103 lines
2.6 KiB
YAML
103 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8 SoC series PCIe PHY
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maintainers:
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- Richard Zhu <hongxing.zhu@nxp.com>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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enum:
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- fsl,imx8mm-pcie-phy
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- fsl,imx8mp-pcie-phy
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: ref
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for iMX8MM
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- const: pciephy
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- items: # for IMX8MP
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- const: pciephy
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- const: perst
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fsl,refclk-pad-mode:
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description: |
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Specifies the mode of the refclk pad used. It can be UNUSED(PHY
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refclock is derived from SoC internal source), INPUT(PHY refclock
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is provided externally via the refclk pad) or OUTPUT(PHY refclock
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is derived from SoC internal source and provided on the refclk pad).
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Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
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to be used.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1, 2 ]
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fsl,tx-deemph-gen1:
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description: Gen1 De-emphasis value (optional).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,tx-deemph-gen2:
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description: Gen2 De-emphasis value (optional).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,clkreq-unsupported:
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type: boolean
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description: A boolean property indicating the CLKREQ# signal is
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not supported in the board design (optional)
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power-domains:
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description: PCIe PHY power domain (optional).
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maxItems: 1
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- fsl,refclk-pad-mode
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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pcie_phy: pcie-phy@32f00000 {
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compatible = "fsl,imx8mm-pcie-phy";
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reg = <0x32f00000 0x10000>;
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clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
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clock-names = "ref";
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
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assigned-clock-rates = <100000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
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resets = <&src IMX8MQ_RESET_PCIEPHY>;
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reset-names = "pciephy";
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
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#phy-cells = <0>;
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};
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...
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