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d761bb01c8
`struct clk_hw_onecell_data` is a flexible structure, which means that
it contains flexible-array member at the bottom, in this case array
`hws`:
include/linux/clk-provider.h:
1380 struct clk_hw_onecell_data {
1381 unsigned int num;
1382 struct clk_hw *hws[] __counted_by(num);
1383 };
This could potentially lead to an overwrite of the objects following
`clk_data` in `struct stratix10_clock_data`, in this case
`void __iomem *base;` at run-time:
drivers/clk/socfpga/stratix10-clk.h:
9 struct stratix10_clock_data {
10 struct clk_hw_onecell_data clk_data;
11 void __iomem *base;
12 };
There are currently three different places where memory is allocated for
`struct stratix10_clock_data`, including the flex-array `hws` in
`struct clk_hw_onecell_data`:
drivers/clk/socfpga/clk-agilex.c:
469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470 num_clks), GFP_KERNEL);
drivers/clk/socfpga/clk-agilex.c:
509 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
510 num_clks), GFP_KERNEL);
drivers/clk/socfpga/clk-s10.c:
400 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
401 num_clks), GFP_KERNEL);
I'll use just one of them to describe the issue. See below.
Notice that a total of 440 bytes are allocated for flexible-array member
`hws` at line 469:
include/dt-bindings/clock/agilex-clock.h:
70 #define AGILEX_NUM_CLKS 55
drivers/clk/socfpga/clk-agilex.c:
459 struct stratix10_clock_data *clk_data;
460 void __iomem *base;
...
466
467 num_clks = AGILEX_NUM_CLKS;
468
469 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
470 num_clks), GFP_KERNEL);
`struct_size(clk_data, clk_data.hws, num_clks)` above translates to
sizeof(struct stratix10_clock_data) + sizeof(struct clk_hw *) * 55 ==
16 + 8 * 55 == 16 + 440
^^^
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allocated bytes for flex-array `hws`
474 for (i = 0; i < num_clks; i++)
475 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
476
477 clk_data->base = base;
and then some data is written into both `hws` and `base` objects.
Fix this by placing the declaration of object `clk_data` at the end of
`struct stratix10_clock_data`. Also, add a comment to make it clear
that this object must always be last in the structure.
-Wflex-array-member-not-at-end is coming in GCC-14, and we are getting
ready to enable it globally.
Fixes: ba7e258425ac ("clk: socfpga: Convert to s10/agilex/n5x to use clk_hw")
Cc: stable@vger.kernel.org
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/1da736106d8e0806aeafa6e471a13ced490eae22.1698117815.git.gustavoars@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#ifndef __STRATIX10_CLK_H
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#define __STRATIX10_CLK_H
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struct stratix10_clock_data {
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void __iomem *base;
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/* Must be last */
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struct clk_hw_onecell_data clk_data;
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};
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struct stratix10_pll_clock {
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unsigned int id;
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const char *name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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};
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struct stratix10_perip_c_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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};
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struct n5x_perip_c_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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const char *const *parent_names;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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unsigned long shift;
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};
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struct stratix10_perip_cnt_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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u8 fixed_divider;
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unsigned long bypass_reg;
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unsigned long bypass_shift;
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};
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struct stratix10_gate_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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unsigned long gate_reg;
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u8 gate_idx;
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unsigned long div_reg;
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u8 div_offset;
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u8 div_width;
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unsigned long bypass_reg;
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u8 bypass_shift;
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u8 fixed_div;
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};
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struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
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void __iomem *reg);
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struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
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void __iomem *reg);
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struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
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void __iomem *reg);
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struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
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void __iomem *reg);
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struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
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void __iomem *reg);
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struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
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void __iomem *reg);
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struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
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void __iomem *reg);
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struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
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void __iomem *reg);
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#endif /* __STRATIX10_CLK_H */
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