Claudiu Beznea 5add5ebc4e clk: renesas: r9a08g045: Add support for power domains ...

Instantiate power domains for the currently enabled IPs of the R9A08G045
SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

2024-04-25 20:12:17 +02:00

..

clk-div6.c

clk: renesas: div6: Implement range checking

2021-05-11 09:58:13 +02:00

clk-div6.h

We have two changes to the core framework this time around. The first being a

2017-11-17 20:04:24 -08:00

clk-emev2.c

clk: renesas: emev2: Remove obsolete clkdev registration

2023-07-27 14:32:41 +02:00

clk-mstp.c

clk: renesas: mstp: Remove obsolete clkdev registration

2024-01-23 21:23:47 +01:00

clk-r8a73a4.c

clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT

2024-04-25 10:38:19 +02:00

clk-r8a7740.c

clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT

2024-04-25 10:38:19 +02:00

clk-r8a7778.c

clk: renesas: r8a7778: Remove struct r8a7778_cpg

2022-06-13 11:53:18 +02:00

clk-r8a7779.c

clk: renesas: r8a7779: Remove struct r8a7779_cpg

2022-06-13 11:53:18 +02:00

clk-rz.c

clk: renesas: rza1: Remove struct rz_cpg

2022-06-13 11:53:18 +02:00

clk-sh73a0.c

clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT

2024-04-25 10:38:19 +02:00

Kconfig

clk: renesas: cpg-mssr: Add support for R-Car V4M

2024-01-31 11:19:21 +01:00

Makefile

clk: renesas: cpg-mssr: Add support for R-Car V4M

2024-01-31 11:19:21 +01:00

r7s9210-cpg-mssr.c

clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag

2020-09-17 15:30:08 +02:00

r8a774a1-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a774b1-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a774c0-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a774e1-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a779a0-cpg-mssr.c

clk: renesas: r8a779a0: Fix CANFD parent clock

2024-04-23 09:35:53 +02:00

r8a779f0-cpg-mssr.c

clk: renesas: r8a779f0: Correct PFC/GPIO parent clock

2024-02-13 17:13:25 +01:00

r8a779g0-cpg-mssr.c

clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks

2024-02-13 17:10:26 +01:00

r8a779h0-cpg-mssr.c

clk: renesas: r8a779h0: Add INTC-EX clock

2024-04-23 09:35:53 +02:00

r8a7742-cpg-mssr.c

clk: renesas: r8a7742: Add clk entry for VSPR

2020-09-04 09:42:01 +02:00

r8a7743-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7745-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7790-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7791-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7792-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7794-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a7795-cpg-mssr.c

clk: renesas: r8a7795: Constify r8a7795_*_clks

2023-09-26 09:38:00 +02:00

r8a7796-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a77470-cpg-mssr.c

clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)

2020-09-04 09:42:01 +02:00

r8a77965-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a77970-cpg-mssr.c

clk: renesas: r8a77970: Add Z2 clock

2023-03-10 17:07:07 +01:00

r8a77980-cpg-mssr.c

clk: renesas: r8a77980: Add I2C5 clock

2023-03-30 16:44:04 +02:00

r8a77990-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r8a77995-cpg-mssr.c

clk: renesas: rcar-gen3: Add ADG clocks

2023-08-15 11:34:43 +02:00

r9a06g032-clocks.c

clk: renesas: r9a06g032: Name anonymous structs

2023-09-18 10:05:23 +02:00

r9a07g043-cpg.c

clk: renesas: r9a07g043: Add clock and reset entry for PLIC

2024-04-23 09:36:49 +02:00

r9a07g044-cpg.c

clk: renesas: r9a07g044: Mark resets array as const

2024-03-26 09:30:44 +01:00

r9a08g045-cpg.c

clk: renesas: r9a08g045: Add support for power domains

2024-04-25 20:12:17 +02:00

r9a09g011-cpg.c

clk: renesas: r9a09g011: Add CSI related clocks

2023-07-10 09:31:53 +02:00

rcar-cpg-lib.c

clk: renesas: rcar-gen3: Extend SDnH divider table

2023-10-05 13:44:34 +02:00

rcar-cpg-lib.h

clk: renesas: rcar-gen3: Switch to new SD clock handling

2021-11-19 11:32:39 +01:00

rcar-gen2-cpg.c

clk: renesas: Zero init clk_init_data

2021-03-30 09:58:27 +02:00

rcar-gen2-cpg.h

clk: renesas: rcar-gen2: Change multipliers and dividers to u8

2019-12-10 10:24:10 +01:00

rcar-gen3-cpg.c

clk: renesas: rcar-gen3: Add support for ZG clock

2023-07-10 09:31:29 +02:00

rcar-gen3-cpg.h

clk: renesas: rcar-gen3: Add support for ZG clock

2023-07-10 09:31:29 +02:00

rcar-gen4-cpg.c

clk: renesas: rcar-gen4: Add support for FRQCRC1

2024-01-31 11:19:21 +01:00

rcar-gen4-cpg.h

clk: renesas: r8a779g0: Add custom clock for PLL2

2023-01-24 10:11:50 +01:00

rcar-usb2-clock-sel.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

renesas-cpg-mssr.c

clk: renesas: cpg-mssr: Add support for R-Car V4M

2024-01-31 11:19:21 +01:00

renesas-cpg-mssr.h

clk: renesas: cpg-mssr: Add support for R-Car V4M

2024-01-31 11:19:21 +01:00

rzg2l-cpg.c

clk: renesas: rzg2l: Extend power domain support

2024-04-25 20:12:15 +02:00

rzg2l-cpg.h

clk: renesas: rzg2l: Extend power domain support

2024-04-25 20:12:15 +02:00