Dinh Nguyen b7f8101d6e clk: socfpga: Fix the smplsel on Arria10 and Stratix10 ...

The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.

Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.

Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2017-06-19 17:01:55 -07:00

..

clk-gate-a10.c

clk: socfpga: Fix the smplsel on Arria10 and Stratix10

2017-06-19 17:01:55 -07:00

clk-gate.c

clk: socfpga: switch to GENMASK()

2015-07-28 11:59:16 -07:00

clk-periph-a10.c

clk: socfpga: allow for multiple parents on Arria10 periph clocks

2016-02-22 14:17:37 -08:00

clk-periph.c

clk: socfpga: Add a second parent option for the dbg_base_clk

2015-08-24 16:49:03 -07:00

clk-pll-a10.c

clk: socfpga: fix __init annotation

2016-02-08 14:13:31 -08:00

clk-pll.c

clk: socfpga: Remove clk.h and clkdev.h includes

2015-07-20 11:11:14 -07:00

clk.c

clk: socfpga: add a clock driver for the Arria 10 platform

2015-05-21 15:16:04 -07:00

clk.h

clk: socfpga: Fix the smplsel on Arria10 and Stratix10

2017-06-19 17:01:55 -07:00

Makefile

clk: socfpga: add a clock driver for the Arria 10 platform

2015-05-21 15:16:04 -07:00