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b41ae49520
Changes since v8: - Corrected license identifiers Changes since v5: - Split up header commit due to size Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/9f1fbf6c18e9644ac10712e05893701f06aee6ae.1700668843.git.donald.robson@imgtec.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
160 lines
5.8 KiB
C
160 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_CR_DEFS_CLIENT_H
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#define PVR_ROGUE_CR_DEFS_CLIENT_H
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/* clang-format off */
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/*
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* This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is
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* provided in both X & Y axis.
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* This register needs to be set based on the ISP Samples Per Pixel a core supports.
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*
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* When ISP Samples Per Pixel = 1:
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* 2xmsaa is achieved by enabling Y - TE does AA on Y plane only
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* 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane
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* 8xmsaa not supported by XE cores
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*
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* When ISP Samples Per Pixel = 2:
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* 2xmsaa is achieved by enabling X2 - does not affect TE
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* 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only
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* 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane
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* 8xmsaa not supported by XE cores
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*
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* When ISP Samples Per Pixel = 4:
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* 2xmsaa is achieved by enabling X2 - does not affect TE
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* 4xmsaa is achieved by enabling Y2 and X2 - TE does AA on Y plane only
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* 8xmsaa not supported by XE cores
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*/
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/* Register ROGUE_CR_TE_AA */
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#define ROGUE_CR_TE_AA 0x0C00U
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#define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full
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/* Y2
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* Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within
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* TPW.
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*/
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#define ROGUE_CR_TE_AA_Y2_SHIFT 3
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#define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF7
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#define ROGUE_CR_TE_AA_Y2_EN 0x00000008
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/* Y
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* Anti-Aliasing in Y Plane Enabled
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*/
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#define ROGUE_CR_TE_AA_Y_SHIFT 2
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#define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB
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#define ROGUE_CR_TE_AA_Y_EN 0x00000004
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/* X
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* Anti-Aliasing in X Plane Enabled
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*/
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#define ROGUE_CR_TE_AA_X_SHIFT 1
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#define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD
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#define ROGUE_CR_TE_AA_X_EN 0x00000002
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/* X2
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* 2x Anti-Aliasing Enabled, affects PPP only
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*/
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#define ROGUE_CR_TE_AA_X2_SHIFT (0U)
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#define ROGUE_CR_TE_AA_X2_CLRMSK (0xFFFFFFFEU)
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#define ROGUE_CR_TE_AA_X2_EN (0x00000001U)
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/* MacroTile Boundaries X Plane */
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/* Register ROGUE_CR_TE_MTILE1 */
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#define ROGUE_CR_TE_MTILE1 0x0C08
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#define ROGUE_CR_TE_MTILE1_MASKFULL 0x0000000007FFFFFFull
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/* X1 default: 0x00000004
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* X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across
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* tile
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*/
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#define ROGUE_CR_TE_MTILE1_X1_SHIFT 18
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#define ROGUE_CR_TE_MTILE1_X1_CLRMSK 0xF803FFFF
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/* X2 default: 0x00000008
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* X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile
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*/
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#define ROGUE_CR_TE_MTILE1_X2_SHIFT 9U
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#define ROGUE_CR_TE_MTILE1_X2_CLRMSK 0xFFFC01FF
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/* X3 default: 0x0000000c
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* X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile
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*/
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#define ROGUE_CR_TE_MTILE1_X3_SHIFT 0
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#define ROGUE_CR_TE_MTILE1_X3_CLRMSK 0xFFFFFE00
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/* MacroTile Boundaries Y Plane. */
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/* Register ROGUE_CR_TE_MTILE2 */
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#define ROGUE_CR_TE_MTILE2 0x0C10
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#define ROGUE_CR_TE_MTILE2_MASKFULL 0x0000000007FFFFFFull
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/* Y1 default: 0x00000004
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* X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile
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* height
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*/
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#define ROGUE_CR_TE_MTILE2_Y1_SHIFT 18
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#define ROGUE_CR_TE_MTILE2_Y1_CLRMSK 0xF803FFFF
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/* Y2 default: 0x00000008
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* X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height
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*/
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#define ROGUE_CR_TE_MTILE2_Y2_SHIFT 9
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#define ROGUE_CR_TE_MTILE2_Y2_CLRMSK 0xFFFC01FF
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/* Y3 default: 0x0000000c
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* X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height
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*/
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#define ROGUE_CR_TE_MTILE2_Y3_SHIFT 0
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#define ROGUE_CR_TE_MTILE2_Y3_CLRMSK 0xFFFFFE00
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/*
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* In order to perform the tiling operation and generate the display list the maximum screen size
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* must be configured in terms of the number of tiles in X & Y axis.
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*/
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/* Register ROGUE_CR_TE_SCREEN */
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#define ROGUE_CR_TE_SCREEN 0x0C18U
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#define ROGUE_CR_TE_SCREEN_MASKFULL 0x00000000001FF1FFull
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/* YMAX default: 0x00000010
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* Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size
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*/
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#define ROGUE_CR_TE_SCREEN_YMAX_SHIFT 12
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#define ROGUE_CR_TE_SCREEN_YMAX_CLRMSK 0xFFE00FFF
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/* XMAX default: 0x00000010
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* Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size
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*/
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#define ROGUE_CR_TE_SCREEN_XMAX_SHIFT 0
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#define ROGUE_CR_TE_SCREEN_XMAX_CLRMSK 0xFFFFFE00
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/*
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* In order to perform the tiling operation and generate the display list the maximum screen size
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* must be configured in terms of the number of pixels in X & Y axis since this may not be the same
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* as the number of tiles defined in the RGX_CR_TE_SCREEN register.
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*/
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/* Register ROGUE_CR_PPP_SCREEN */
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#define ROGUE_CR_PPP_SCREEN 0x0C98
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#define ROGUE_CR_PPP_SCREEN_MASKFULL 0x000000007FFF7FFFull
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/* PIXYMAX
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* Screen height in pixels. (16K x 16K max screen size)
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*/
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#define ROGUE_CR_PPP_SCREEN_PIXYMAX_SHIFT 16
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#define ROGUE_CR_PPP_SCREEN_PIXYMAX_CLRMSK 0x8000FFFF
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/* PIXXMAX
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* Screen width in pixels.(16K x 16K max screen size)
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*/
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#define ROGUE_CR_PPP_SCREEN_PIXXMAX_SHIFT 0
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#define ROGUE_CR_PPP_SCREEN_PIXXMAX_CLRMSK 0xFFFF8000
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/* Register ROGUE_CR_ISP_MTILE_SIZE */
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#define ROGUE_CR_ISP_MTILE_SIZE 0x0F18
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#define ROGUE_CR_ISP_MTILE_SIZE_MASKFULL 0x0000000003FF03FFull
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/* X
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* Macrotile width, in tiles. A value of zero corresponds to the maximum size
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*/
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#define ROGUE_CR_ISP_MTILE_SIZE_X_SHIFT 16
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#define ROGUE_CR_ISP_MTILE_SIZE_X_CLRMSK 0xFC00FFFF
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#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSHIFT 0
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#define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSIZE 1
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/* Y
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* Macrotile height, in tiles. A value of zero corresponds to the maximum size
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*/
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#define ROGUE_CR_ISP_MTILE_SIZE_Y_SHIFT 0
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#define ROGUE_CR_ISP_MTILE_SIZE_Y_CLRMSK 0xFFFFFC00
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#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSHIFT 0
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#define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSIZE 1
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/* clang-format on */
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#endif /* PVR_ROGUE_CR_DEFS_CLIENT_H */
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