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40ba17afdf
A cxl_decoder is a child of a cxl_port. It represents a hardware decoder
configuration of an upstream port to one or more of its downstream
ports. The decoder is either represented in CXL standard HDM decoder
registers (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder Capability
Structure), or it is a static decode configuration communicated by
platform firmware (see the CXL Early Discovery Table: Fixed Memory
Window Structure).
The firmware described and hardware described decoders differ slightly
leading to 2 different sub-types of decoders, cxl_decoder_root and
cxl_decoder_switch. At the root level the decode capabilities restrict
what can be mapped beneath them. Mid-level switch decoders are
configured for either acclerator (type-2) or memory-expander (type-3)
operation, but they are otherwise agnostic to the type of memory
(volatile vs persistent) being mapped.
Here is an example topology from a single-ported host-bridge environment
without CFMWS decodes enumerated.
/sys/bus/cxl/devices/root0
├── devtype
├── dport0 -> ../../../LNXSYSTM:00/LNXSYBUS:00/ACPI0016:00
├── port1
│ ├── decoder1.0
│ │ ├── devtype
│ │ ├── locked
│ │ ├── size
│ │ ├── start
│ │ ├── subsystem -> ../../../../../../bus/cxl
│ │ ├── target_list
│ │ ├── target_type
│ │ └── uevent
│ ├── devtype
│ ├── dport0 -> ../../../../pci0000:34/0000:34:00.0
│ ├── subsystem -> ../../../../../bus/cxl
│ ├── uevent
│ └── uport -> ../../../../LNXSYSTM:00/LNXSYBUS:00/ACPI0016:00
├── subsystem -> ../../../../bus/cxl
├── uevent
└── uport -> ../../ACPI0017:00
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162325695128.2293823.17519927266014762694.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
265 lines
8.3 KiB
C
265 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. */
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#ifndef __CXL_H__
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#define __CXL_H__
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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/**
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* DOC: cxl objects
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*
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* The CXL core objects like ports, decoders, and regions are shared
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* between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
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* (port-driver, region-driver, nvdimm object-drivers... etc).
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*/
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/* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
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#define CXL_CM_OFFSET 0x1000
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#define CXL_CM_CAP_HDR_OFFSET 0x0
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#define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
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#define CM_CAP_HDR_CAP_ID 1
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#define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
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#define CM_CAP_HDR_CAP_VERSION 1
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#define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
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#define CM_CAP_HDR_CACHE_MEM_VERSION 1
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#define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
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#define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
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#define CXL_CM_CAP_CAP_ID_HDM 0x5
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#define CXL_CM_CAP_CAP_HDM_VERSION 1
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/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
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#define CXL_HDM_DECODER_CAP_OFFSET 0x0
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#define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
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#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
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#define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10
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#define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14
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#define CXL_HDM_DECODER0_SIZE_LOW_OFFSET 0x18
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#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c
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#define CXL_HDM_DECODER0_CTRL_OFFSET 0x20
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/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
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#define CXLDEV_CAP_ARRAY_OFFSET 0x0
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#define CXLDEV_CAP_ARRAY_CAP_ID 0
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#define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
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/* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
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#define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
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/* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
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#define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
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#define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
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#define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
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#define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
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/* CXL 2.0 8.2.8.4 Mailbox Registers */
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#define CXLDEV_MBOX_CAPS_OFFSET 0x00
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#define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
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#define CXLDEV_MBOX_CTRL_OFFSET 0x04
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#define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
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#define CXLDEV_MBOX_CMD_OFFSET 0x08
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#define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
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#define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
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#define CXLDEV_MBOX_STATUS_OFFSET 0x10
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#define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
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#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
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#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
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#define CXL_COMPONENT_REGS() \
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void __iomem *hdm_decoder
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#define CXL_DEVICE_REGS() \
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void __iomem *status; \
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void __iomem *mbox; \
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void __iomem *memdev
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/* See note for 'struct cxl_regs' for the rationale of this organization */
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/*
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* CXL_COMPONENT_REGS - Common set of CXL Component register block base pointers
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* @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
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*/
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struct cxl_component_regs {
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CXL_COMPONENT_REGS();
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};
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/* See note for 'struct cxl_regs' for the rationale of this organization */
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/*
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* CXL_DEVICE_REGS - Common set of CXL Device register block base pointers
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* @status: CXL 2.0 8.2.8.3 Device Status Registers
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* @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
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* @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
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*/
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struct cxl_device_regs {
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CXL_DEVICE_REGS();
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};
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/*
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* Note, the anonymous union organization allows for per
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* register-block-type helper routines, without requiring block-type
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* agnostic code to include the prefix.
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*/
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struct cxl_regs {
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union {
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struct {
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CXL_COMPONENT_REGS();
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};
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struct cxl_component_regs component;
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};
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union {
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struct {
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CXL_DEVICE_REGS();
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};
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struct cxl_device_regs device_regs;
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};
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};
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struct cxl_reg_map {
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bool valid;
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unsigned long offset;
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unsigned long size;
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};
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struct cxl_component_reg_map {
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struct cxl_reg_map hdm_decoder;
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};
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struct cxl_device_reg_map {
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struct cxl_reg_map status;
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struct cxl_reg_map mbox;
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struct cxl_reg_map memdev;
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};
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struct cxl_register_map {
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struct list_head list;
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u64 block_offset;
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u8 reg_type;
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u8 barno;
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union {
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struct cxl_component_reg_map component_map;
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struct cxl_device_reg_map device_map;
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};
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};
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void cxl_probe_component_regs(struct device *dev, void __iomem *base,
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struct cxl_component_reg_map *map);
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void cxl_probe_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_reg_map *map);
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int cxl_map_component_regs(struct pci_dev *pdev,
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struct cxl_component_regs *regs,
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struct cxl_register_map *map);
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int cxl_map_device_regs(struct pci_dev *pdev,
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struct cxl_device_regs *regs,
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struct cxl_register_map *map);
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#define CXL_RESOURCE_NONE ((resource_size_t) -1)
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#define CXL_TARGET_STRLEN 20
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/*
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* cxl_decoder flags that define the type of memory / devices this
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* decoder supports as well as configuration lock status See "CXL 2.0
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* 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
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*/
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#define CXL_DECODER_F_RAM BIT(0)
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#define CXL_DECODER_F_PMEM BIT(1)
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#define CXL_DECODER_F_TYPE2 BIT(2)
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#define CXL_DECODER_F_TYPE3 BIT(3)
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#define CXL_DECODER_F_LOCK BIT(4)
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#define CXL_DECODER_F_MASK GENMASK(4, 0)
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enum cxl_decoder_type {
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CXL_DECODER_ACCELERATOR = 2,
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CXL_DECODER_EXPANDER = 3,
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};
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/**
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* struct cxl_decoder - CXL address range decode configuration
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* @dev: this decoder's device
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* @id: kernel device name id
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* @range: address range considered by this decoder
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* @interleave_ways: number of cxl_dports in this decode
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* @interleave_granularity: data stride per dport
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* @target_type: accelerator vs expander (type2 vs type3) selector
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* @flags: memory type capabilities and locking
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* @target: active ordered target list in current decoder configuration
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*/
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struct cxl_decoder {
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struct device dev;
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int id;
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struct range range;
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int interleave_ways;
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int interleave_granularity;
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enum cxl_decoder_type target_type;
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unsigned long flags;
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struct cxl_dport *target[];
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};
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/**
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* struct cxl_port - logical collection of upstream port devices and
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* downstream port devices to construct a CXL memory
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* decode hierarchy.
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* @dev: this port's device
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* @uport: PCI or platform device implementing the upstream port capability
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* @id: id for port device-name
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* @dports: cxl_dport instances referenced by decoders
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* @decoder_ida: allocator for decoder ids
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* @component_reg_phys: component register capability base address (optional)
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*/
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struct cxl_port {
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struct device dev;
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struct device *uport;
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int id;
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struct list_head dports;
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struct ida decoder_ida;
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resource_size_t component_reg_phys;
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};
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/**
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* struct cxl_dport - CXL downstream port
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* @dport: PCI bridge or firmware device representing the downstream link
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* @port_id: unique hardware identifier for dport in decoder target list
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* @component_reg_phys: downstream port component registers
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* @port: reference to cxl_port that contains this downstream port
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* @list: node for a cxl_port's list of cxl_dport instances
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*/
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struct cxl_dport {
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struct device *dport;
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int port_id;
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resource_size_t component_reg_phys;
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struct cxl_port *port;
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struct list_head list;
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};
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struct cxl_port *to_cxl_port(struct device *dev);
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struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
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resource_size_t component_reg_phys,
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struct cxl_port *parent_port);
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int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
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resource_size_t component_reg_phys);
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struct cxl_decoder *to_cxl_decoder(struct device *dev);
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struct cxl_decoder *
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devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
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resource_size_t base, resource_size_t len,
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int interleave_ways, int interleave_granularity,
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enum cxl_decoder_type type, unsigned long flags);
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/*
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* Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
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* single ported host-bridges need not publish a decoder capability when a
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* passthrough decode can be assumed, i.e. all transactions that the uport sees
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* are claimed and passed to the single dport. Default the range a 0-base
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* 0-length until the first CXL region is activated.
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*/
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static inline struct cxl_decoder *
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devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port)
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{
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return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE,
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CXL_DECODER_EXPANDER, 0);
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}
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extern struct bus_type cxl_bus_type;
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#endif /* __CXL_H__ */
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