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550064a85b
QCM2290 can support two memory configurations: single-channel, 32-bit wide LPDDR3 @ up to 933MHz (bus clock) or dual-channel, 16-bit wide LPDDR4X @ up to 1804 MHz. The interconnect driver in its current form seems to gravitate towards the first one, however there are no LPDDR3- equipped boards upstream and we still don't have a great way to discern the DDR generations on the kernel side. To make DDR scaling possible on the only currently-supported 2290 board, stick with the LPDDR4X config by default. The side effect on any potential LPDDR3 board would be that the requested bus clock rate is too high (but still capped to the firmware-configured FMAX). Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-7-c04b60caa467@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org> |
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| .. | ||
| imx | ||
| qcom | ||
| samsung | ||
| bulk.c | ||
| core.c | ||
| debugfs-client.c | ||
| icc-clk.c | ||
| internal.h | ||
| Kconfig | ||
| Makefile | ||
| trace.h | ||