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b1dcfe6205
The latest released firmware supports reading firmware interface version from registers directly. The driver's probe routine reads the major and minor version numbers. If the firmware interface is not compatible with the driver, the driver's probe routine returns failure. Co-developed-by: Min Ma <min.ma@amd.com> Signed-off-by: Min Ma <min.ma@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213232933.1545388-5-lizhi.hou@amd.com
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/amdxdna_accel.h>
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#include <drm/drm_device.h>
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#include <drm/gpu_scheduler.h>
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#include <linux/sizes.h>
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#include "aie2_pci.h"
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#include "amdxdna_mailbox.h"
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#include "amdxdna_pci_drv.h"
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/* Address definition from NPU1 docs */
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#define MPNPU_PUB_SEC_INTR 0x3010090
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#define MPNPU_PUB_PWRMGMT_INTR 0x3010094
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#define MPNPU_PUB_SCRATCH2 0x30100A0
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#define MPNPU_PUB_SCRATCH3 0x30100A4
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#define MPNPU_PUB_SCRATCH4 0x30100A8
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#define MPNPU_PUB_SCRATCH5 0x30100AC
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#define MPNPU_PUB_SCRATCH6 0x30100B0
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#define MPNPU_PUB_SCRATCH7 0x30100B4
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#define MPNPU_PUB_SCRATCH9 0x30100BC
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#define MPNPU_SRAM_X2I_MAILBOX_0 0x30A0000
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#define MPNPU_SRAM_X2I_MAILBOX_1 0x30A2000
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#define MPNPU_SRAM_I2X_MAILBOX_15 0x30BF000
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#define MPNPU_APERTURE0_BASE 0x3000000
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#define MPNPU_APERTURE1_BASE 0x3080000
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#define MPNPU_APERTURE2_BASE 0x30C0000
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/* PCIe BAR Index for NPU1 */
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#define NPU1_REG_BAR_INDEX 0
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#define NPU1_MBOX_BAR_INDEX 4
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#define NPU1_PSP_BAR_INDEX 0
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#define NPU1_SMU_BAR_INDEX 0
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#define NPU1_SRAM_BAR_INDEX 2
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/* Associated BARs and Apertures */
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#define NPU1_REG_BAR_BASE MPNPU_APERTURE0_BASE
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#define NPU1_MBOX_BAR_BASE MPNPU_APERTURE2_BASE
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#define NPU1_PSP_BAR_BASE MPNPU_APERTURE0_BASE
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#define NPU1_SMU_BAR_BASE MPNPU_APERTURE0_BASE
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#define NPU1_SRAM_BAR_BASE MPNPU_APERTURE1_BASE
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const struct rt_config npu1_default_rt_cfg[] = {
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{ 2, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */
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{ 1, 1, AIE2_RT_CFG_CLK_GATING }, /* Clock gating on */
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{ 0 },
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};
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const struct dpm_clk_freq npu1_dpm_clk_table[] = {
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{400, 800},
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{600, 1024},
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{600, 1024},
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{600, 1024},
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{600, 1024},
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{720, 1309},
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{720, 1309},
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{847, 1600},
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{ 0 }
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};
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const struct amdxdna_dev_priv npu1_dev_priv = {
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.fw_path = "amdnpu/1502_00/npu.sbin",
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.protocol_major = 0x5,
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.protocol_minor = 0x7,
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.rt_config = npu1_default_rt_cfg,
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.dpm_clk_tbl = npu1_dpm_clk_table,
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.col_align = COL_ALIGN_NONE,
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.mbox_dev_addr = NPU1_MBOX_BAR_BASE,
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.mbox_size = 0, /* Use BAR size */
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.sram_dev_addr = NPU1_SRAM_BAR_BASE,
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.sram_offs = {
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DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
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DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),
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},
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.psp_regs_off = {
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DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
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DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),
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DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU1_PSP, MPNPU_PUB_SCRATCH4),
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DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU1_PSP, MPNPU_PUB_SCRATCH9),
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DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU1_PSP, MPNPU_PUB_SEC_INTR),
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DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2),
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DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3),
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},
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.smu_regs_off = {
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DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU1_SMU, MPNPU_PUB_SCRATCH5),
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DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),
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DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU1_SMU, MPNPU_PUB_PWRMGMT_INTR),
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DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU1_SMU, MPNPU_PUB_SCRATCH6),
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DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU1_SMU, MPNPU_PUB_SCRATCH7),
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},
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.hw_ops = {
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.set_dpm = npu1_set_dpm,
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},
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};
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const struct amdxdna_dev_info dev_npu1_info = {
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.reg_bar = NPU1_REG_BAR_INDEX,
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.mbox_bar = NPU1_MBOX_BAR_INDEX,
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.sram_bar = NPU1_SRAM_BAR_INDEX,
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.psp_bar = NPU1_PSP_BAR_INDEX,
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.smu_bar = NPU1_SMU_BAR_INDEX,
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.first_col = 1,
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.dev_mem_buf_shift = 15, /* 32 KiB aligned */
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.dev_mem_base = AIE2_DEVM_BASE,
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.dev_mem_size = AIE2_DEVM_SIZE,
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.vbnv = "RyzenAI-npu1",
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.device_type = AMDXDNA_DEV_TYPE_KMQ,
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.dev_priv = &npu1_dev_priv,
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.ops = &aie2_ops,
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};
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