Robert Richter 5d2ffbe4b8 cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport ... Same as for ports, also store the downstream port's Component Register mappings, use struct cxl_dport for that. Signed-off-by: Robert Richter <rrichter@amd.com> Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230622205523.85375-16-terry.bowman@amd.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-06-25 12:22:53 -07:00
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core	cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport	2023-06-25 12:22:53 -07:00
acpi.c	cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port	2023-06-25 11:41:45 -07:00
cxl.h	cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport	2023-06-25 12:22:53 -07:00
cxlmem.h	cxl: Rename 'uport' to 'uport_dev'	2023-06-25 11:37:54 -07:00
cxlpci.h	cxl: Wait Memory_Info_Valid before access memory related info	2023-05-18 16:42:41 -07:00
Kconfig	Merge branch 'for-6.3/cxl-ram-region' into cxl/next	2023-02-10 18:11:01 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
mem.c	cxl/pci: Early setup RCH dport component registers from RCRB	2023-06-25 11:57:11 -07:00
pci.c	cxl/pci: Early setup RCH dport component registers from RCRB	2023-06-25 11:57:11 -07:00
pmem.c	cxl/pmem: Fix nvdimm registration races	2023-02-13 17:01:05 -08:00
port.c	cxl/regs: Remove early capability checks in Component Register setup	2023-06-25 11:51:36 -07:00
security.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00