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History

Will Simoneau 1ef48593bd sparc: sun4m SMP: fix wrong shift instruction in IPI handler

This shift instruction appears to be shifting in the wrong direction.
Without this change, my SparcStation-20MP hangs just after bringing up
the second CPU:

Entering SMP Mode...
Starting CPU 2 at f02b4e90
Brought up 2 CPUs
Total of 2 processors activated (99.52 BogoMIPS).
   *** stuck ***

Signed-off-by: Will Simoneau <simoneau@ele.uri.edu>
Signed-off-by: David S. Miller <davem@davemloft.net>

2011-07-16 10:45:12 -07:00

boot

sparc32: added U-Boot build target: uImage

2011-03-16 18:19:04 -07:00

configs

defconfig reduction

2010-08-14 22:26:53 +02:00

include/asm

sparc/irqs: Do not trace arch_local_{*,irq_*} functions

2011-07-06 08:00:29 -07:00

kernel

sparc: sun4m SMP: fix wrong shift instruction in IPI handler