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90893b90d3
After the PHY has powered and initialized, it needs some delay for controller to reflect PHY's status. Some status and values for id, vbus, dp/dm are only stable after this delay. The current code tries to clear id/vbus status without enough delay, it causes the status are not cleared properly. This patch add 2ms delay after phy has initialized, and clear the unexpected status after that. Signed-off-by: Peter Chen <peter.chen@freescale.com> Tested-by: Li Jun <b47624@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>