Zhang Rui 931da6a0de powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR ... On Sapphire Rapids, the layout of the Psys domain Power Limit Register is different from from what it was before. Enhance the code to support the new Psys PL register layout. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reported-and-tested-by: Alkattan Dana <dana.alkattan@intel.com> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>		2021-12-17 16:13:14 +01:00
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dtpm_cpu.c	powercap: DTPM: Fix suspend failure and kernel warning	2021-11-10 21:18:14 +01:00
dtpm.c	powercap: DTPM: Drop unused local variable from init_dtpm()	2021-12-03 17:51:59 +01:00
idle_inject.c	powercap: include header to fix -Wmissing-prototypes	2020-09-25 16:46:01 +02:00
intel_rapl_common.c	powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR	2021-12-17 16:13:14 +01:00
intel_rapl_msr.c	powercap: Add Power Limit4 support for Alder Lake SoC	2021-08-25 20:12:16 +02:00
Kconfig	powercap/drivers/dtpm: Add the experimental label to the option description	2021-03-01 17:43:29 +01:00
Makefile	powercap/drivers/dtpm: Add CPU energy model based support	2020-12-22 19:50:40 +01:00
powercap_sys.c	Merge branches 'pm-sleep', 'pm-acpi', 'pm-domains' and 'powercap'	2020-12-15 15:26:14 +01:00