Keith Packard ba1eb1d825 i915: Map status page cached for chips with GTT-based HWS location. ...

This should improve performance by avoiding uncached reads by the CPU (the
point of having a status page), and may improve stability.  This patch only
affects G33, GM45 and G45 chips as those are the only ones using GTT-based
HWS mappings.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

2008-10-18 07:10:53 +10:00

..

drm

i915: Map status page cached for chips with GTT-based HWS location.

2008-10-18 07:10:53 +10:00

Makefile

drm: reorganise drm tree to be more future proof.

2008-07-14 10:45:01 +10:00