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e7a8386941
A100 features an updated DPHY, which moves PLL control inside the DPHY register space. (Previously PLL-MIPI was controlled from the CCU. This does not affect the "clocks" property because the link between PLL-MIPI and the DPHY was never represented in the devicetree.) It also requires a modified analog power-on sequence. Finally, the new DPHY adds support for operating as an LVDS PHY. D1 uses this same variant. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221114022113.31694-5-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
85 lines
1.7 KiB
YAML
85 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 MIPI D-PHY Controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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oneOf:
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- const: allwinner,sun6i-a31-mipi-dphy
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- const: allwinner,sun50i-a100-mipi-dphy
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- items:
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- const: allwinner,sun50i-a64-mipi-dphy
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- const: allwinner,sun6i-a31-mipi-dphy
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- items:
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- const: allwinner,sun20i-d1-mipi-dphy
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- const: allwinner,sun50i-a100-mipi-dphy
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: bus
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- const: mod
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resets:
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maxItems: 1
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allwinner,direction:
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$ref: '/schemas/types.yaml#/definitions/string'
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description: |
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Direction of the D-PHY:
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- "rx" for receiving (e.g. when used with MIPI CSI-2);
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- "tx" for transmitting (e.g. when used with MIPI DSI).
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enum:
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- tx
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- rx
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default: tx
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required:
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- "#phy-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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dphy0: d-phy@1ca1000 {
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compatible = "allwinner,sun6i-a31-mipi-dphy";
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reg = <0x01ca1000 0x1000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 23>, <&ccu 97>;
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clock-names = "bus", "mod";
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resets = <&ccu 4>;
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#phy-cells = <0>;
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};
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...
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