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NXP SC16C2552 requires that we always write a reset to the RX FIFO and TX FIFO whenever we enable the FIFOs Cc: xe-kernel@external.cisco.com Signed-off-by: Steve Shih <sshih@cisco.com> Signed-off-by: David Singleton <davsingl@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>