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History

Hans-Christian Egtvedt 35bf50ccc8 avr32: Implement set_rate(), set_parent() and mode() for pll1

This patch is a take two of adding full functionality to PLL1 on
AT32AP7000.  This allows board-specific code and drivers to configure
and enable PLL1. This is useful when precise control over the
frequency of e.g. a genclock is needed and requested by users for the
ABDAC device.

The patch is based upon previous patches from both Haavard Skinnemoen
and David Brownell.

Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

2008-04-19 20:40:08 -04:00

at32ap700x.c

avr32: Implement set_rate(), set_parent() and mode() for pll1

2008-04-19 20:40:08 -04:00

at32ap.c

[AVR32] Split SM device into PM, RTC, WDT and EIC

2007-07-18 20:45:51 +02:00

clock.c

[AVR32] /sys/kernel/debug/at32ap_clk

2007-10-11 11:38:41 +02:00

clock.h

[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories