Petlozu Pravareshwar c9c4ddb20c soc/tegra: pmc: Add I/O pad table for Tegra234 ...

Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.

On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.

While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.

Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
[treding@nvidia.com: generate tables from tegra-pinmux-scripts]
Signed-off-by: Thierry Reding <treding@nvidia.com>

2022-11-10 02:21:12 +01:00

..

ahb.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

bpmp-abi.h

soc/tegra: bpmp: cleanup double word in comment

2022-02-25 14:10:09 +01:00

bpmp.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

common.h

soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()

2021-12-16 14:03:38 +01:00

cpuidle.h

cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle

2020-03-13 11:31:58 +01:00

flowctrl.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 399

2019-06-05 17:37:12 +02:00

fuse.h

soc/tegra: Set ERD bit to mask inband errors

2022-09-15 12:30:11 +02:00

irq.h

soc/tegra: irq: Add stubs needed for compile testing

2021-10-04 21:27:21 +02:00

ivc.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

mc.h

memory: tegra: Add MC error logging on Tegra186 onward

2022-05-09 10:46:14 +02:00

pm.h

soc/tegra: pm: Make stubs usable for compile testing

2021-10-04 21:27:40 +02:00

pmc.h

soc/tegra: pmc: Add I/O pad table for Tegra234

2022-11-10 02:21:12 +01:00

tegra-cbb.h

soc/tegra: cbb: Add CBB 1.0 driver for Tegra194

2022-09-15 12:41:36 +02:00