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ccd6a13180
In order to be able to deal with the MMU enabled and the MMU disabled cases, the base address of the coherency registers was passed to the function. The address by itself was not interesting as it can't change for a given SoC, the only thing we need is to have a distinction between the physical or the virtual address. This patch add a check of the MMU bit to choose the accurate address, then the calling function doesn't have to pass this information. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
77 lines
1.6 KiB
ArmAsm
77 lines
1.6 KiB
ArmAsm
/*
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* Coherency fabric: low level functions
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file implements the assembly function to add a CPU to the
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* coherency fabric. This function is called by each of the secondary
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* CPUs during their early boot in an SMP kernel, this why this
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* function have to callable from assembly. It can also be called by a
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* primary CPU from C code during its boot.
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*/
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#include <linux/linkage.h>
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#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
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#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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.text
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/*
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* r0: HW CPU id
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*/
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ENTRY(ll_set_cpu_coherent)
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mrc p15, 0, r1, c1, c0, 0
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tst r1, #CR_M @ Check MMU bit enabled
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bne 1f
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/* use physical address of the coherency register*/
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adr r0, 3f
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ldr r3, [r0]
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ldr r0, [r0, r3]
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b 2f
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1:
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/* use virtual address of the coherency register*/
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ldr r0, =coherency_base
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ldr r0, [r0]
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2:
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/* Create bit by cpu index */
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mov r3, #(1 << 24)
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lsl r1, r3, r1
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ARM_BE8(rev r1, r1)
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/* Add CPU to SMP group - Atomic */
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add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
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1:
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ldrex r2, [r3]
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orr r2, r2, r1
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strex r0, r2, [r3]
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cmp r0, #0
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bne 1b
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/* Enable coherency on CPU - Atomic */
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add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
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1:
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ldrex r2, [r3]
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orr r2, r2, r1
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strex r0, r2, [r3]
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cmp r0, #0
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bne 1b
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dsb
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mov r0, #0
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mov pc, lr
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ENDPROC(ll_set_cpu_coherent)
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.align 2
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3:
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.long coherency_phys_base - .
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