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84c49aac0e
Update the Marvell 88e6185 PCS driver to use neg_mode rather than the mode argument to match the other updated PCS drivers. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/E1rhosE-003yuc-FM@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
192 lines
4.1 KiB
C
192 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Marvell 88E6185 family SERDES PCS support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
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*/
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#include <linux/phylink.h>
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#include "global2.h"
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#include "port.h"
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#include "serdes.h"
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struct mv88e6185_pcs {
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struct phylink_pcs phylink_pcs;
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unsigned int irq;
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char name[64];
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struct mv88e6xxx_chip *chip;
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int port;
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};
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static struct mv88e6185_pcs *pcs_to_mv88e6185_pcs(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mv88e6185_pcs, phylink_pcs);
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}
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static irqreturn_t mv88e6185_pcs_handle_irq(int irq, void *dev_id)
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{
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struct mv88e6185_pcs *mpcs = dev_id;
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struct mv88e6xxx_chip *chip;
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irqreturn_t ret = IRQ_NONE;
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bool link_up;
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u16 status;
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int port;
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int err;
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chip = mpcs->chip;
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port = mpcs->port;
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
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mv88e6xxx_reg_unlock(chip);
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if (!err) {
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link_up = !!(status & MV88E6XXX_PORT_STS_LINK);
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phylink_pcs_change(&mpcs->phylink_pcs, link_up);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static void mv88e6185_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct mv88e6185_pcs *mpcs = pcs_to_mv88e6185_pcs(pcs);
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struct mv88e6xxx_chip *chip = mpcs->chip;
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int port = mpcs->port;
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u16 status;
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int err;
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mv88e6xxx_reg_lock(chip);
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
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mv88e6xxx_reg_unlock(chip);
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if (err)
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status = 0;
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state->link = !!(status & MV88E6XXX_PORT_STS_LINK);
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if (state->link) {
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state->duplex = status & MV88E6XXX_PORT_STS_DUPLEX ?
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DUPLEX_FULL : DUPLEX_HALF;
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switch (status & MV88E6XXX_PORT_STS_SPEED_MASK) {
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case MV88E6XXX_PORT_STS_SPEED_1000:
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state->speed = SPEED_1000;
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break;
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case MV88E6XXX_PORT_STS_SPEED_100:
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state->speed = SPEED_100;
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break;
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case MV88E6XXX_PORT_STS_SPEED_10:
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state->speed = SPEED_10;
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break;
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default:
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state->link = false;
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break;
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}
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}
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}
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static int mv88e6185_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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return 0;
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}
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static void mv88e6185_pcs_an_restart(struct phylink_pcs *pcs)
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{
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}
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static const struct phylink_pcs_ops mv88e6185_phylink_pcs_ops = {
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.pcs_get_state = mv88e6185_pcs_get_state,
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.pcs_config = mv88e6185_pcs_config,
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.pcs_an_restart = mv88e6185_pcs_an_restart,
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};
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static int mv88e6185_pcs_init(struct mv88e6xxx_chip *chip, int port)
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{
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struct mv88e6185_pcs *mpcs;
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struct device *dev;
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unsigned int irq;
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int err;
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/* There are no configurable serdes lanes on this switch chip, so
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* we use the static cmode configuration to determine whether we
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* have a PCS or not.
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*/
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if (chip->ports[port].cmode != MV88E6185_PORT_STS_CMODE_SERDES &&
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chip->ports[port].cmode != MV88E6185_PORT_STS_CMODE_1000BASE_X)
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return 0;
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dev = chip->dev;
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mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
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if (!mpcs)
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return -ENOMEM;
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mpcs->chip = chip;
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mpcs->port = port;
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mpcs->phylink_pcs.ops = &mv88e6185_phylink_pcs_ops;
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mpcs->phylink_pcs.neg_mode = true;
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irq = mv88e6xxx_serdes_irq_mapping(chip, port);
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if (irq) {
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snprintf(mpcs->name, sizeof(mpcs->name),
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"mv88e6xxx-%s-serdes-%d", dev_name(dev), port);
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err = request_threaded_irq(irq, NULL, mv88e6185_pcs_handle_irq,
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IRQF_ONESHOT, mpcs->name, mpcs);
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if (err) {
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kfree(mpcs);
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return err;
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}
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mpcs->irq = irq;
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} else {
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mpcs->phylink_pcs.poll = true;
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}
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chip->ports[port].pcs_private = &mpcs->phylink_pcs;
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return 0;
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}
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static void mv88e6185_pcs_teardown(struct mv88e6xxx_chip *chip, int port)
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{
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struct mv88e6185_pcs *mpcs;
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mpcs = chip->ports[port].pcs_private;
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if (!mpcs)
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return;
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if (mpcs->irq)
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free_irq(mpcs->irq, mpcs);
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kfree(mpcs);
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chip->ports[port].pcs_private = NULL;
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}
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static struct phylink_pcs *mv88e6185_pcs_select(struct mv88e6xxx_chip *chip,
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int port,
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phy_interface_t interface)
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{
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return chip->ports[port].pcs_private;
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}
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const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops = {
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.pcs_init = mv88e6185_pcs_init,
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.pcs_teardown = mv88e6185_pcs_teardown,
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.pcs_select = mv88e6185_pcs_select,
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};
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