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7867e40278
* Support for sv48 paging. * Hart ID mappings are now sparse, which enables more CPUs to come up on systems with sparse hart IDs. * A handful of cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmHq5KQTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiY+yEACrEgyrb/YBVxmO8q2L4eodF4J/coxz g5pZkmZeZkGKkhpk7jrf+/P+7iLgT9x+EFzinofl4/QZeSeVHZyawiHpNUa72JUS Pk1hs2EpfQafbXgpSKGL6HLyJXESe/kzX31s4PJudNz7GcQBAL54hYCrTb79lmXX FQPVYZ71EZhGupRkSyTI1Bmp2wjdwy00Lto3/pQ5zZkVoLX7yyoL5XGDFqtNF+vI tiHXzWY5+TYDFhV+g6f8x9kIbqr7H7Gk2MzzOYoSp3jgOTTPGlnjXVOjWiCv5WWH 6tt2fas4tlV4t4gPqIrDUQtkc3gvvfMSHY9gwid9kZKd8RNT2NoHjkLLeRqmcMZZ 4R7Gu/QKmulZvnjQ99mxcdhrg9xse+FG7WqDeQykaLpGo9UBqQ9of+L5z7Mt9T23 vn62G5qeH7AOrMNWdR0PWCQPFQlRibxpvVvzEVhgg+uUK19ReicHAgTEE/457E81 Rx/f8zb3PbaAnmQEhPs8IVXJo6AXSzZQiUTD3KRJXNeYa4scHaVKGVY9RQQ9tDcH tJKUXHumITrLxxgxTktYHPTBgtoDvjYMGv/iSSJDkrScpWW1tsXadbm3ma6cPxQJ DQO+o/J8+DqWLFbwVZ93oL/19uZHth6y43kBocZJuVetg27a3CD5PutQWoqrbGjV m5oedHdFW1Oouw== =WKqE -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.17-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for sv48 paging - Hart ID mappings are now sparse, which enables more CPUs to come up on systems with sparse hart IDs - A handful of cleanups and fixes * tag 'riscv-for-linus-5.17-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (27 commits) RISC-V: nommu_virt: Drop unused SLAB_MERGE_DEFAULT RISC-V: Remove redundant err variable riscv: dts: sifive unmatched: Add gpio poweroff riscv: canaan: remove useless select of non-existing config SYSCON RISC-V: Do not use cpumask data structure for hartid bitmap RISC-V: Move spinwait booting method to its own config RISC-V: Move the entire hart selection via lottery to SMP RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method RISC-V: Do not print the SBI version during HSM extension boot print RISC-V: Avoid using per cpu array for ordered booting riscv: default to CONFIG_RISCV_SBI_V01=n riscv: fix boolconv.cocci warnings riscv: Explicit comment about user virtual address space size riscv: Use pgtable_l4_enabled to output mmu_type in cpuinfo riscv: Implement sv48 support asm-generic: Prepare for riscv use of pud_alloc_one and pud_free riscv: Allow to dynamically define VA_BITS riscv: Introduce functions to switch pt_ops riscv: Split early kasan mapping to prepare sv48 introduction riscv: Move KASAN mapping next to the kernel mapping ... |
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