Andrew Vasquez dcb36ce9d9 [SCSI] qla2xxx: Correct additional posting issues during NVRAM accesses.
On MMIO relaxed-order platforms, it is possible for the
proper delay during NVRAM access to begin before the request
passes through the PCI bus (via a MMIO write) to the ISP.
Thus, causing a subsequent read to the NVRAM part to fail.
Add a MMIO read, after the MMIO write to insure any posted
writes are flushed.

Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
2005-11-09 16:17:25 -05:00
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