Rongjun Ying 89e162afd3 ARM: CSR: initializing L2 cache ...

Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>

2011-07-09 07:21:53 +08:00

..

include/mach

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00

clock.c

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00

common.h

ARM: CSR: mapping early DEBUG_LL uart

2011-07-09 07:20:51 +08:00

irq.c

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00

l2x0.c

ARM: CSR: initializing L2 cache

2011-07-09 07:21:53 +08:00

lluart.c

ARM: CSR: mapping early DEBUG_LL uart

2011-07-09 07:20:51 +08:00

Makefile

ARM: CSR: initializing L2 cache

2011-07-09 07:21:53 +08:00

Makefile.boot

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00

prima2.c

ARM: CSR: mapping early DEBUG_LL uart

2011-07-09 07:20:51 +08:00

rstc.c

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00

timer.c

ARM: CSR: Adding CSR SiRFprimaII board support

2011-07-09 07:19:28 +08:00