mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-14 09:47:20 +00:00
a5f6ea29f9
Commit bcf24e1daa94 ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.
sh-allmodconfig now fails with:
include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1
This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h. There's a similar issue with "CCR2"
on sh2a.
As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
|
|
* include/asm-sh/cpu-sh4/cache.h
|
|
*
|
|
* Copyright (C) 1999 Niibe Yutaka
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*/
|
|
#ifndef __ASM_CPU_SH4_CACHE_H
|
|
#define __ASM_CPU_SH4_CACHE_H
|
|
|
|
#define L1_CACHE_SHIFT 5
|
|
|
|
#define SH_CACHE_VALID 1
|
|
#define SH_CACHE_UPDATED 2
|
|
#define SH_CACHE_COMBINED 4
|
|
#define SH_CACHE_ASSOC 8
|
|
|
|
#define SH_CCR 0xff00001c /* Address of Cache Control Register */
|
|
#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
|
|
#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
|
|
#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
|
|
#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
|
|
#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
|
|
#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
|
|
#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
|
|
#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
|
|
#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
|
|
#ifndef CONFIG_CPU_SH4A
|
|
#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
|
|
#endif
|
|
|
|
/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
|
|
#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
|
|
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
|
|
|
|
#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
|
|
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
|
|
|
|
#define RAMCR 0xFF000074
|
|
|
|
#endif /* __ASM_CPU_SH4_CACHE_H */
|
|
|