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ef87bd81cb
The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20221114230217.202634-4-dinguyen@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>