mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-09 07:23:14 +00:00
c23be918c5
Prabhakar <prabhakar.csengg@gmail.com> says:
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
non-coherent DMA support for AX45MP
====================================
On the Andes AX45MP core, cache coherency is a specification option so it
may not be supported. In this case DMA will fail. To get around with this
issue this patch series does the below:
1] Andes alternative ports is implemented as errata which checks if the
IOCP is missing and only then applies to CMO errata. One vendor specific
SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of
errata.
Below are the configs which Andes port provides (and are selected by
RZ/Five):
- ERRATA_ANDES
- ERRATA_ANDES_CMO
OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now
part v1.3 release.
2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
OpenSBI configures the PMA regions as required and creates a reserve memory
node and propagates it to the higher boot stack.
Currently OpenSBI (upstream) configures the required PMA region and passes
this a shared DMA pool to Linux.
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pma_resv0@58000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x58000000 0x0 0x08000000>;
no-map;
linux,dma-default;
};
};
The above shared DMA pool gets appended to Linux DTB so the DMA memory
requests go through this region.
3] We provide callbacks to synchronize specific content between memory and
cache.
4] RZ/Five SoC selects the below configs
- AX45MP_L2_CACHE
- DMA_GLOBAL_POOL
- ERRATA_ANDES
- ERRATA_ANDES_CMO
----------x---------------------x--------------------x---------------x----
* b4-shazam-merge:
soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
cache: Add L2 cache management for Andes AX45MP RISC-V core
dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
riscv: mm: dma-noncoherent: nonstandard cache operations support
riscv: errata: Add Andes alternative ports
riscv: asm: vendorid_list: Add Andes Technology to the vendors list
Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (C) 2021 Sifive.
|
|
*/
|
|
|
|
#ifndef __ASM_ALTERNATIVE_H
|
|
#define __ASM_ALTERNATIVE_H
|
|
|
|
#include <asm/alternative-macros.h>
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#ifdef CONFIG_RISCV_ALTERNATIVE
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/types.h>
|
|
#include <linux/stddef.h>
|
|
#include <asm/hwcap.h>
|
|
|
|
#define PATCH_ID_CPUFEATURE_ID(p) lower_16_bits(p)
|
|
#define PATCH_ID_CPUFEATURE_VALUE(p) upper_16_bits(p)
|
|
|
|
#define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */
|
|
#define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */
|
|
#define RISCV_ALTERNATIVES_EARLY_BOOT 2 /* alternatives applied before mmu start */
|
|
|
|
/* add the relative offset to the address of the offset to get the absolute address */
|
|
#define __ALT_PTR(a, f) ((void *)&(a)->f + (a)->f)
|
|
#define ALT_OLD_PTR(a) __ALT_PTR(a, old_offset)
|
|
#define ALT_ALT_PTR(a) __ALT_PTR(a, alt_offset)
|
|
|
|
void __init apply_boot_alternatives(void);
|
|
void __init apply_early_boot_alternatives(void);
|
|
void apply_module_alternatives(void *start, size_t length);
|
|
|
|
void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,
|
|
int patch_offset);
|
|
|
|
struct alt_entry {
|
|
s32 old_offset; /* offset relative to original instruction or data */
|
|
s32 alt_offset; /* offset relative to replacement instruction or data */
|
|
u16 vendor_id; /* CPU vendor ID */
|
|
u16 alt_len; /* The replacement size */
|
|
u32 patch_id; /* The patch ID (erratum ID or cpufeature ID) */
|
|
};
|
|
|
|
void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
|
|
unsigned long archid, unsigned long impid,
|
|
unsigned int stage);
|
|
void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
|
|
unsigned long archid, unsigned long impid,
|
|
unsigned int stage);
|
|
void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
|
|
unsigned long archid, unsigned long impid,
|
|
unsigned int stage);
|
|
|
|
void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end,
|
|
unsigned int stage);
|
|
|
|
#else /* CONFIG_RISCV_ALTERNATIVE */
|
|
|
|
static inline void apply_boot_alternatives(void) { }
|
|
static inline void apply_early_boot_alternatives(void) { }
|
|
static inline void apply_module_alternatives(void *start, size_t length) { }
|
|
|
|
#endif /* CONFIG_RISCV_ALTERNATIVE */
|
|
|
|
#endif
|
|
#endif
|