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[MIPS] Malta: Fix reading the PCI clock frequency on big-endian

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The JMPRS register on Malta boards keeps a 32-bit CPU-endian
value. The readw() function assumes that the value it reads is a
little-endian 16-bit number. Therefore, using readw() to obtain
the value of the JMPRS register is a mistake. This error leads
to incorrect reading of the PCI clock frequency on big-endian
during board start-up.

Change readw() to __raw_readl().

This was tested by injecting a call to printk() and verifying
that the value of the jmpr variable was consistent with current
setting of the JP4 "PCI CLK" jumper.

Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Dmitri Vorobiev 2008-01-15 00:27:46 +03:00 committed by Ralf Baechle
parent c2a04c4f0e
commit 0487de9142
1 changed files with 1 additions and 1 deletions
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2
arch/mips/mips-boards/malta/malta_setup.c
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@ -149,7 +149,7 @@ void __init plat_mem_setup(void)
/* Check PCI clock */
{
unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
int jmpr = (readw(jmpr_p) >> 2) & 0x07;
int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
static const int pciclocks[] __initdata = {
33, 20, 25, 30, 12, 16, 37, 10
};