Merge branch 'pci/dt-bindings'

- Update mediatek-gen3 DT binding to require the exact number of clocks for
  each SoC (Fei Shao)

- Add qcom SAR2130P DT binding with an additional clock (Dmitry Baryshkov)

* pci/dt-bindings:
  dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example
  dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
  dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only

Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

@@ -149,7 +149,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          minItems: 6
 
         clock-names:
           items:
@@ -178,7 +178,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          minItems: 6
 
         clock-names:
           items:
@@ -207,6 +207,7 @@ allOf:
       properties:
         clocks:
           minItems: 4
+          maxItems: 4
 
         clock-names:
           items:

Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml

@@ -20,6 +20,7 @@ properties:
       - const: qcom,pcie-sm8550
       - items:
           - enum:
+              - qcom,sar2130p-pcie
               - qcom,pcie-sm8650
           - const: qcom,pcie-sm8550
 
@@ -39,7 +40,7 @@ properties:
 
   clocks:
     minItems: 7
-    maxItems: 8
+    maxItems: 9
 
   clock-names:
     minItems: 7
@@ -52,6 +53,7 @@ properties:
       - const: ddrss_sf_tbu # PCIe SF TBU clock
       - const: noc_aggr # Aggre NoC PCIe AXI clock
       - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
+      - const: qmip_pcie_ahb # QMIP PCIe AHB clock
 
   interrupts:
     minItems: 8

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

@@ -230,7 +230,6 @@ examples:
 
       interrupts = <25>, <24>;
       interrupt-names = "msi", "hp";
-      #interrupt-cells = <1>;
 
       reset-gpios = <&port0 0 1>;