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soundwire: intel: add support for MeteorLake additional clocks

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In the MeteorLake hardware, the SoundWire link clock can be selected
from the Xtal, audio cardinal clock (24.576 MHz) or the 96 MHz audio
PLL.

This patches add the clock selection in a backwards-compatible manner,
using the ACPI firmware as the source of information and checking its
compatibility with hardware capabilities.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20240326092030.1062802-5-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2024-03-26 09:20:27 +00:00 committed by Vinod Koul
parent d0a69cd036
commit 09ee49e3de
2 changed files with 42 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
drivers/soundwire/intel.c
View File

@ -345,8 +345,10 @@ static int intel_link_power_up(struct sdw_intel *sdw)
u32 spa_mask, cpa_mask;
u32 link_control;
int ret = 0;
u32 clock_source;
u32 syncprd;
u32 sync_reg;
bool lcap_mlcs;
mutex_lock(sdw->link_res->shim_lock);
@ -358,12 +360,35 @@ static int intel_link_power_up(struct sdw_intel *sdw)
* is only dependent on the oscillator clock provided to
* the IP, so adjust based on _DSD properties reported in DSDT
* tables. The values reported are based on either 24MHz
* (CNL/CML) or 38.4 MHz (ICL/TGL+).
* (CNL/CML) or 38.4 MHz (ICL/TGL+). On MeteorLake additional
* frequencies are available with the MLCS clock source selection.
*/
if (prop->mclk_freq % 6000000)
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
else
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
lcap_mlcs = intel_readl(shim, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_MLCS_MASK;
if (prop->mclk_freq % 6000000) {
if (prop->mclk_freq % 2400000) {
if (lcap_mlcs) {
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576;
clock_source = SDW_SHIM_MLCS_CARDINAL_CLK;
} else {
dev_err(sdw->cdns.dev, "%s: invalid clock configuration, mclk %d lcap_mlcs %d\n",
__func__, prop->mclk_freq, lcap_mlcs);
ret = -EINVAL;
goto out;
}
} else {
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
clock_source = SDW_SHIM_MLCS_XTAL_CLK;
}
} else {
if (lcap_mlcs) {
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96;
clock_source = SDW_SHIM_MLCS_AUDIO_PLL_CLK;
} else {
syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
clock_source = SDW_SHIM_MLCS_XTAL_CLK;
}
}
if (!*shim_mask) {
dev_dbg(sdw->cdns.dev, "powering up all links\n");
@ -403,6 +428,13 @@ static int intel_link_power_up(struct sdw_intel *sdw)
"Failed to set SHIM_SYNC: %d\n", ret);
goto out;
}
/* update link clock if needed */
if (lcap_mlcs) {
link_control = intel_readl(shim, SDW_SHIM_LCTL);
u32p_replace_bits(&link_control, clock_source, SDW_SHIM_LCTL_MLCS_MASK);
intel_writel(shim, SDW_SHIM_LCTL, link_control);
}
}
*shim_mask |= BIT(link_id);
@ -1087,4 +1119,3 @@ const struct sdw_intel_hw_ops sdw_intel_cnl_hw_ops = {
.sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked,
};
EXPORT_SYMBOL_NS(sdw_intel_cnl_hw_ops, SOUNDWIRE_INTEL);

5
include/linux/soundwire/sdw_intel.h
View File

@ -22,6 +22,7 @@
/* LCAP */
#define SDW_SHIM_LCAP 0x0
#define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
#define SDW_SHIM_LCAP_MLCS_MASK BIT(8)
/* LCTL */
#define SDW_SHIM_LCTL 0x4
@ -30,6 +31,10 @@
#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
#define SDW_SHIM_LCTL_CPA BIT(8)
#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
#define SDW_SHIM_LCTL_MLCS_MASK GENMASK(29, 27)
#define SDW_SHIM_MLCS_XTAL_CLK 0x0
#define SDW_SHIM_MLCS_CARDINAL_CLK 0x1
#define SDW_SHIM_MLCS_AUDIO_PLL_CLK 0x2
/* SYNC */
#define SDW_SHIM_SYNC 0xC