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arm64/ptrace: add support for FEAT_POE
Add a regset for POE containing POR_EL0. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20240822151113.1479789-21-joey.gouly@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -1440,6 +1440,39 @@ static int tagged_addr_ctrl_set(struct task_struct *target, const struct
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}
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#endif
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#ifdef CONFIG_ARM64_POE
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static int poe_get(struct task_struct *target,
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const struct user_regset *regset,
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struct membuf to)
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{
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if (!system_supports_poe())
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return -EINVAL;
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return membuf_write(&to, &target->thread.por_el0,
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sizeof(target->thread.por_el0));
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}
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static int poe_set(struct task_struct *target, const struct
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user_regset *regset, unsigned int pos,
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unsigned int count, const void *kbuf, const
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void __user *ubuf)
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{
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int ret;
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long ctrl;
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if (!system_supports_poe())
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return -EINVAL;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1);
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if (ret)
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return ret;
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target->thread.por_el0 = ctrl;
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return 0;
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}
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#endif
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enum aarch64_regset {
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REGSET_GPR,
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REGSET_FPR,
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@ -1469,6 +1502,9 @@ enum aarch64_regset {
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#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
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REGSET_TAGGED_ADDR_CTRL,
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#endif
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#ifdef CONFIG_ARM64_POE
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REGSET_POE
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#endif
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};
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static const struct user_regset aarch64_regsets[] = {
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@ -1628,6 +1664,16 @@ static const struct user_regset aarch64_regsets[] = {
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.set = tagged_addr_ctrl_set,
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},
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#endif
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#ifdef CONFIG_ARM64_POE
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[REGSET_POE] = {
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.core_note_type = NT_ARM_POE,
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.n = 1,
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.size = sizeof(long),
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.align = sizeof(long),
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.regset_get = poe_get,
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.set = poe_set,
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},
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#endif
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};
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static const struct user_regset_view user_aarch64_view = {
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@ -441,6 +441,7 @@ typedef struct elf64_shdr {
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#define NT_ARM_ZA 0x40c /* ARM SME ZA registers */
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#define NT_ARM_ZT 0x40d /* ARM SME ZT registers */
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#define NT_ARM_FPMR 0x40e /* ARM floating point mode register */
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#define NT_ARM_POE 0x40f /* ARM POE registers */
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#define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */
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#define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */
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#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
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