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net/mlx5: Fix MTMP register capability offset in MCAM register

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The MTMP register (0x900a) capability offset is off-by-one, move it to
the right place.

Fixes: 1f507e80c700 ("net/mlx5: Expose NIC temperature via hardware monitoring kernel API")
Signed-off-by: Gal Pressman <gal@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Gal Pressman 2024-05-22 22:26:54 +03:00 committed by David S. Miller
parent fca3b47918
commit 1b9f86c6d5
1 changed files with 2 additions and 2 deletions
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4
include/linux/mlx5/mlx5_ifc.h
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@ -10308,9 +10308,9 @@ struct mlx5_ifc_mcam_access_reg_bits {
u8 mfrl[0x1];
u8 regs_39_to_32[0x8];
u8 regs_31_to_10[0x16];
u8 regs_31_to_11[0x15];
u8 mtmp[0x1];
u8 regs_8_to_0[0x9];
u8 regs_9_to_0[0xa];
};
struct mlx5_ifc_mcam_access_reg_bits1 {