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clk: eyeq: add EyeQ6H west fixed factor clocks

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Previous setup was:
 - pll-west clock registered from driver at of_clk_init();
 - Both OCC and UART clocks registered from DT using fixed-factor-clock
   compatible.

Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use
that capability to register west-per-occ and west-per-uart (giving them
proper names at the same time).

Also switch from hard-coded index 0 for pll-west to using the
EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers.

All get exposed at of_clk_init() because they get used by the AMBA PL011
serial ports. Those are instantiated before platform bus infrastructure.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-8-84cfefb3f485@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Théo Lebrun 2024-11-06 17:03:59 +01:00 committed by Stephen Boyd
parent 0b28f9ee4b
commit 1cbdfcfd08
1 changed files with 9 additions and 1 deletions
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10
drivers/clk/clk-eyeq.c
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@ -712,12 +712,20 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i
/* Required early for UART. */
static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
{ .index = 0, .name = "pll-west", .reg64 = 0x074 },
{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 },
};
static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
{ EQ6HC_WEST_PER_OCC, "west-per-occ", 1, 10, EQ6HC_WEST_PLL_PER },
{ EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1, EQ6HC_WEST_PER_OCC },
};
static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = {
.early_pll_count = ARRAY_SIZE(eqc_eyeq6h_west_early_plls),
.early_plls = eqc_eyeq6h_west_early_plls,
.early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors),
.early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors,
};
static void __init eqc_early_init(struct device_node *np,