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firmware: zynqmp: Add MMIO read and write support for PS_MODE pin
Add Xilinx ZynqMP firmware MMIO APIs support to set and get PS_MODE pins value and status. These APIs create an interface path between mode pin controller driver and low-level API to access GPIO pins. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
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@ -28,6 +28,13 @@
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/* Max HashMap Order for PM API feature check (1<<7 = 128) */
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#define PM_API_FEATURE_CHECK_MAX_ORDER 7
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/* CRL registers and bitfields */
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#define CRL_APB_BASE 0xFF5E0000U
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/* BOOT_PIN_CTRL- Used to control the mode pins after boot */
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#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + (0x250U))
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/* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
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#define CRL_APB_BOOTPIN_CTRL_MASK 0xF0FU
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static bool feature_check_enabled;
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static DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER);
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@ -925,6 +932,45 @@ int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);
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/**
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* zynqmp_pm_bootmode_read() - PM Config API for read bootpin status
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* @ps_mode: Returned output value of ps_mode
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*
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* This API function is to be used for notify the power management controller
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* to read bootpin status.
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*
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* Return: status, either success or error+reason
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*/
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unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
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{
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unsigned int ret;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, CRL_APB_BOOT_PIN_CTRL, 0,
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0, 0, ret_payload);
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*ps_mode = ret_payload[1];
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_read);
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/**
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* zynqmp_pm_bootmode_write() - PM Config API for Configure bootpin
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* @ps_mode: Value to be written to the bootpin ctrl register
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*
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* This API function is to be used for notify the power management controller
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* to configure bootpin.
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*
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* Return: Returns status, either success or error+reason
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*/
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int zynqmp_pm_bootmode_write(u32 ps_mode)
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{
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return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, CRL_APB_BOOT_PIN_CTRL,
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CRL_APB_BOOTPIN_CTRL_MASK, ps_mode, 0, NULL);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write);
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/**
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* zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
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* master has initialized its own power management
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@ -72,6 +72,8 @@ enum pm_api_id {
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PM_SET_REQUIREMENT = 15,
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PM_RESET_ASSERT = 17,
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PM_RESET_GET_STATUS = 18,
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PM_MMIO_WRITE = 19,
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PM_MMIO_READ = 20,
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PM_PM_INIT_FINALIZE = 21,
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PM_FPGA_LOAD = 22,
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PM_FPGA_GET_STATUS = 23,
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@ -390,6 +392,8 @@ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
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int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
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const enum zynqmp_pm_reset_action assert_flag);
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int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
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unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
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int zynqmp_pm_bootmode_write(u32 ps_mode);
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int zynqmp_pm_init_finalize(void);
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int zynqmp_pm_set_suspend_mode(u32 mode);
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int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
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@ -520,6 +524,16 @@ static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
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return -ENODEV;
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}
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static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_init_finalize(void)
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{
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return -ENODEV;
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