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x86/entry: __always_inline CR2 for noinstr
vmlinux.o: warning: objtool: exc_page_fault()+0x9: call to read_cr2() leaves .noinstr.text section vmlinux.o: warning: objtool: exc_page_fault()+0x24: call to prefetchw() leaves .noinstr.text section vmlinux.o: warning: objtool: exc_page_fault()+0x21: call to kvm_handle_async_pf.isra.0() leaves .noinstr.text section vmlinux.o: warning: objtool: exc_nmi()+0x1cc: call to write_cr2() leaves .noinstr.text section Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20200603114052.243227806@infradead.org
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@ -141,7 +141,7 @@ static inline void kvm_disable_steal_time(void)
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return;
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}
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static inline bool kvm_handle_async_pf(struct pt_regs *regs, u32 token)
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static __always_inline bool kvm_handle_async_pf(struct pt_regs *regs, u32 token)
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{
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return false;
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}
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@ -823,7 +823,7 @@ static inline void prefetch(const void *x)
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* Useful for spinlocks to avoid one state transition in the
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* cache coherency protocol:
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*/
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static inline void prefetchw(const void *x)
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static __always_inline void prefetchw(const void *x)
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{
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alternative_input(BASE_PREFETCH, "prefetchw %P1",
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X86_FEATURE_3DNOWPREFETCH,
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@ -28,14 +28,14 @@ static inline unsigned long native_read_cr0(void)
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return val;
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}
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static inline unsigned long native_read_cr2(void)
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static __always_inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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static __always_inline void native_write_cr2(unsigned long val)
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{
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asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
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}
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@ -160,12 +160,12 @@ static inline void write_cr0(unsigned long x)
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native_write_cr0(x);
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}
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static inline unsigned long read_cr2(void)
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static __always_inline unsigned long read_cr2(void)
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{
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return native_read_cr2();
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}
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static inline void write_cr2(unsigned long x)
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static __always_inline void write_cr2(unsigned long x)
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{
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native_write_cr2(x);
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}
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