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riscv: Add CSR definitions for pointer masking
Pointer masking is controlled via a two-bit PMM field, which appears in various CSRs depending on which extensions are implemented. Smmpm adds the field to mseccfg; Smnpm adds the field to menvcfg; Ssnpm adds the field to senvcfg. If the H extension is implemented, Ssnpm also defines henvcfg.PMM and hstatus.HUPMM. Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20241016202814.4061541-4-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -119,6 +119,10 @@
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/* HSTATUS flags */
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#ifdef CONFIG_64BIT
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#define HSTATUS_HUPMM _AC(0x3000000000000, UL)
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#define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL)
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#define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL)
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#define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL)
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#define HSTATUS_VSXL _AC(0x300000000, UL)
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#define HSTATUS_VSXL_SHIFT 32
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#endif
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@ -195,6 +199,10 @@
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/* xENVCFG flags */
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#define ENVCFG_STCE (_AC(1, ULL) << 63)
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#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
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#define ENVCFG_PMM (_AC(0x3, ULL) << 32)
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#define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32)
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#define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32)
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#define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32)
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#define ENVCFG_CBZE (_AC(1, UL) << 7)
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#define ENVCFG_CBCFE (_AC(1, UL) << 6)
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#define ENVCFG_CBIE_SHIFT 4
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@ -216,6 +224,12 @@
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#define SMSTATEEN0_SSTATEEN0_SHIFT 63
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#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
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/* mseccfg bits */
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#define MSECCFG_PMM ENVCFG_PMM
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#define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0
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#define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7
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#define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16
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/* symbolic CSR names: */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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@ -382,6 +396,8 @@
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPADDR0 0x3b0
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#define CSR_MSECCFG 0x747
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#define CSR_MSECCFGH 0x757
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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