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irqchip/mips-gic: Add a IPI hierarchy domain
Add a new ipi domain on top of the normal domain. MIPS GIC now supports dynamic allocation of an IPI. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: <jason@lakedaemon.net> Cc: <marc.zyngier@arm.com> Cc: <jiang.liu@linux.intel.com> Cc: <linux-mips@linux-mips.org> Cc: <lisa.parratt@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Link: http://lkml.kernel.org/r/1449580830-23652-13-git-send-email-qais.yousef@imgtec.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Qais Yousef
Thomas Gleixner
parent
3b8e29a82d
commit
2af70a9620
@ -209,6 +209,7 @@ config KEYSTONE_IRQ
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config MIPS_GIC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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config INGENIC_IRQ
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@ -29,16 +29,31 @@ struct gic_pcpu_mask {
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DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
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};
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struct gic_irq_spec {
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enum {
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GIC_DEVICE,
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GIC_IPI
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} type;
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union {
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struct cpumask *ipimask;
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unsigned int hwirq;
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};
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};
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static unsigned long __gic_base_addr;
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static void __iomem *gic_base;
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static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
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static DEFINE_SPINLOCK(gic_lock);
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static struct irq_domain *gic_irq_domain;
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static struct irq_domain *gic_ipi_domain;
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static int gic_shared_intrs;
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static int gic_vpes;
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static unsigned int gic_cpu_pin;
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static unsigned int timer_cpu_pin;
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static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
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DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
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static void __gic_irq_dispatch(void);
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@ -753,7 +768,7 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
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}
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static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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irq_hw_number_t hw, unsigned int vpe)
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{
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int intr = GIC_HWIRQ_TO_SHARED(hw);
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unsigned long flags;
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@ -763,9 +778,8 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
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spin_lock_irqsave(&gic_lock, flags);
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gic_map_to_pin(intr, gic_cpu_pin);
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/* Map to VPE 0 by default */
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gic_map_to_vpe(intr, 0);
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set_bit(intr, pcpu_masks[0].pcpu_mask);
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gic_map_to_vpe(intr, vpe);
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set_bit(intr, pcpu_masks[vpe].pcpu_mask);
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spin_unlock_irqrestore(&gic_lock, flags);
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return 0;
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@ -776,7 +790,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
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{
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if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
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return gic_local_irq_domain_map(d, virq, hw);
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return gic_shared_irq_domain_map(d, virq, hw);
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return gic_shared_irq_domain_map(d, virq, hw, 0);
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}
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static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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@ -798,9 +812,157 @@ static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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return 0;
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}
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static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct gic_irq_spec *spec = arg;
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irq_hw_number_t hwirq, base_hwirq;
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int cpu, ret, i;
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if (spec->type == GIC_DEVICE) {
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/* verify that it doesn't conflict with an IPI irq */
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if (test_bit(spec->hwirq, ipi_resrv))
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return -EBUSY;
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} else {
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base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs);
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if (base_hwirq == gic_shared_intrs) {
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return -ENOMEM;
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}
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/* check that we have enough space */
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for (i = base_hwirq; i < nr_irqs; i++) {
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if (!test_bit(i, ipi_resrv))
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return -EBUSY;
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}
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bitmap_clear(ipi_resrv, base_hwirq, nr_irqs);
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/* map the hwirq for each cpu consecutively */
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i = 0;
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for_each_cpu(cpu, spec->ipimask) {
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hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
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ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
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&gic_edge_irq_controller,
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NULL);
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if (ret)
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goto error;
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ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
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if (ret)
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goto error;
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i++;
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}
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/*
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* tell the parent about the base hwirq we allocated so it can
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* set its own domain data
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*/
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spec->hwirq = base_hwirq;
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}
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return 0;
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error:
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bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
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return ret;
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}
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void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs)
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{
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irq_hw_number_t base_hwirq;
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struct irq_data *data;
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data = irq_get_irq_data(virq);
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if (!data)
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return;
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base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
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bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
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}
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static const struct irq_domain_ops gic_irq_domain_ops = {
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.map = gic_irq_domain_map,
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.xlate = gic_irq_domain_xlate,
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.alloc = gic_irq_domain_alloc,
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.free = gic_irq_domain_free,
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};
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static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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/*
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* There's nothing to translate here. hwirq is dynamically allocated and
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* the irq type is always edge triggered.
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* */
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*out_hwirq = 0;
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*out_type = IRQ_TYPE_EDGE_RISING;
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return 0;
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}
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static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct cpumask *ipimask = arg;
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struct gic_irq_spec spec = {
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.type = GIC_IPI,
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.ipimask = ipimask
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};
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int ret, i;
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ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec);
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if (ret)
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return ret;
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/* the parent should have set spec.hwirq to the base_hwirq it allocated */
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for (i = 0; i < nr_irqs; i++) {
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ret = irq_domain_set_hwirq_and_chip(d, virq + i,
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GIC_SHARED_TO_HWIRQ(spec.hwirq + i),
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&gic_edge_irq_controller,
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NULL);
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if (ret)
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goto error;
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ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
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if (ret)
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goto error;
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}
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return 0;
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error:
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irq_domain_free_irqs_parent(d, virq, nr_irqs);
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return ret;
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}
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void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs)
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{
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irq_domain_free_irqs_parent(d, virq, nr_irqs);
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}
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int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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bool is_ipi;
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switch (bus_token) {
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case DOMAIN_BUS_IPI:
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is_ipi = d->bus_token == bus_token;
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return to_of_node(d->fwnode) == node && is_ipi;
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break;
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default:
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return 0;
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}
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}
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static struct irq_domain_ops gic_ipi_domain_ops = {
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.xlate = gic_ipi_domain_xlate,
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.alloc = gic_ipi_domain_alloc,
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.free = gic_ipi_domain_free,
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.match = gic_ipi_domain_match,
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};
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static void __init __gic_init(unsigned long gic_base_addr,
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@ -864,6 +1026,18 @@ static void __init __gic_init(unsigned long gic_base_addr,
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if (!gic_irq_domain)
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panic("Failed to add GIC IRQ domain");
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gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
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IRQ_DOMAIN_FLAG_IPI_PER_CPU,
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GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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node, &gic_ipi_domain_ops, NULL);
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if (!gic_ipi_domain)
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panic("Failed to add GIC IPI domain");
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gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
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/* Make the last 2 * NR_CPUS available for IPIs */
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bitmap_set(ipi_resrv, gic_shared_intrs - 2 * NR_CPUS, 2 * NR_CPUS);
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gic_basic_init();
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gic_ipi_init();
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