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clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent

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Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
This commit is contained in:
AngeloGioacchino Del Regno 2022-09-27 12:11:27 +02:00 committed by Chen-Yu Tsai
parent 72d38ed720
commit 341d2035fa
1 changed files with 4 additions and 2 deletions
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6
drivers/clk/mediatek/clk-mt8192-mfg.c
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@ -18,8 +18,10 @@ static const struct mtk_gate_regs mfg_cg_regs = {
.sta_ofs = 0x0, .sta_ofs = 0x0,
}; };
#define GATE_MFG(_id, _name, _parent, _shift) \ #define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
_shift, &mtk_clk_gate_ops_setclr, \
CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = { static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0), GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),